• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.3
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• pp.1105-1120
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• 2015

With the proposed principle of two-dimensional matrix bar code design based on masks, the whole surface of a 2D bar code is used for creating graphic patterns. Masks are a method of overlaying certain information with complete preservation of encoded information. In order to ensure suitable mask performance, it is essential to create a set of masks (mask folder) which are similar to each other. This ultimately allows additional error correction on the whole code level which is proven mathematically through an academic example of a QR code with a matrix of size $9{\times}9$. In order to create a mask folder, this article will investigate parameters based on Weber's law. With the parameters founded in the research, this principle shows how QR codes, or any other 2D bar code, can be designed to display two different messages. This ultimately enables a better description of a 2D bar code, which will improve users' visual recognition of 2D bar code purpose, and therefore users' greater enjoyment and involvement.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.99-102
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• 2002

In this work, we evaluated the performance of soft iterative decoder with soft block decoder in optical storage system. Because optical storage system requires run- length limited code in general, adaptation of the soft decoders such as turbo code or LDPC(low density parity check code) is difficult without soft block decoders. The performance of the overall optical detection system is evaluated and the simplified channel detection is also proposed.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2008.11a
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• pp.690-693
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• 2008

Recently, the trend has been for buildings to become larger and more sophisticated, and this has created safety issues. Because the buildings are big it takes lots of time to check building codes related to anti-disaster and safety manually, and there is the high possibility of making mistakes. Due to these problems, according to a study, 83% of architecture and construction workers believe that an automated code-checking system is needed. This study researches past automated code checking systems and research activity, and using Building Information Model (BIM) technology, determines the feasibility of developing a system to automatically check domestic codes related to egress and anti-disaster. This paper describes the necessity of an automated building code checking system and expected effects. It then reports whether the methods used in previous studies can be deployed in domestic building code checking and discusses problems and limitations. It also suggests an alternative approach. Although this study covers limited codes related to egress, we need to find out what is needed for automatic general code checking system and do further studies for that.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.10
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• pp.2411-2429
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• 2013

In this paper, we extend the case of information exchange error mitigation for the distributed orthogonal space-time block code (DOSTBC) for two transmit antennas to distributed quasi-orthogonal space-time block code (DQOSTBC) for four transmit antennas. A rate 1 full-diversity DQOSTBC for four transmit antennas is designed. The code matrix changes according to different information exchange error cases, so full diversity is maintained even if not all information exchange is correct. We also perform analysis of the pairwise error probability. The performance analysis indicates that the proposed rate 1 DQOSTBC outperforms rate 1/2 DOSTBC for four transmit antennas at the same transmission rate, which is confirmed by the simulation results.

• Journal of KIISE:Software and Applications
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• v.32 no.4
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• pp.290-299
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• 2005

Stealing the source code of a program is a serious problem not only in a moral sense but also in a legal sense. However, it is not clear whether the code of a program is copied from another or not. There was a program similarity checker detecting code-copy by comparing the syntax trees of programs. However this method has a limitation that it cannot detect the code-copy attacks when the attacker modifies the syntax of the program on purpose. We propose a program similarity check by program control graph, which reveals not only syntax information but also control dependancy. Our method can detect the code-copy attacks that do not change control dependancy Moreover, we define what code-copy means and establish the connection between code-copy and similarity of program control graph: we prove that two programs are related by copy congruence if and only if the program control graphs of these programs are equivalent. We implemented our method on a functional programming language, nML. The experimental results show us that the suggested method can detect code similarity that is not detected by the existing method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of Communications and Networks
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• v.17 no.2
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• pp.157-161
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• 2015

A new block low-density parity-check (Block-LDPC) code based on quadratic permutation polynomials (QPPs) is proposed. The parity-check matrix of the Block-LDPC code is composed of a group of permutation submatrices that correspond to QPPs. The scheme provides a large range of implementable LDPC codes. Indeed, the most popular quasi-cyclic LDPC (QC-LDPC) codes are just a subset of this scheme. Simulation results indicate that the proposed scheme can offer similar error performance and implementation complexity as the popular QC-LDPC codes.

• Journal of KIISE:Software and Applications
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• v.32 no.7
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• pp.683-692
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• 2005

Java specification states that all accesses to an object must be checked at runtime if object refers to null. Since Java is an object-oriented language, object accesses are frequent enough to make null pointer checks affect the performance significantly. In order to reduce the performance degradation, there have been attempts to remove redundant null pointer checks. For example, in a Java environment where a just-in-time (JIT) compiler is used, the JIT compiler removes redundant null pointer check code via code analysis. This paper proposes a technique to remove additional null pointer check code that could not be removed by previous JIT compilation techniques, via early null pointer check using an architectural feature called predication. Generally, null point check code consists of two instructions: a compare and a branch. Our idea is moving the compare instruction that is usually located just before an use of an object, to the point right after the object is defined so that the total number of compare instructions is reduced. This results in reduction of dynamic and static compare instructions by 3.21$\%$ and 1.98$\%$. respectively, in SPECjvm98 bechmarks, compared to the code that has already been optimized by previous null pointer check elimination techniques. Its performance impact on an Itanium machine is an improvement of 0.32$\%$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.