• The Journal of the Acoustical Society of Korea
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• v.37 no.4
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• pp.215-222
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• 2018

This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.108-115
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• 2011

Virtual Robot Education System (VRES), which is for programming education with a Lego Mindstorm NXT robot, is designed and implemented. Through this system, program learners can edit source code, compile, download it into the robot, and run their executive program. In order to observe it, the system includes web cameras and provide monitoring services. Thus, students are able to verify the operation of robot into which they download their program in detail and to debug if necessary. In addition, we design a new simple user-friendly programming language and a corresponding compiler for it. With those tools, learner can more easily create programs for NXT robot and test them than Java language. A educator can control and manage the robot for the subject of a class with direct control mode of our system. Therefore, the proposed system is able to support students to learn robot programming during or after regular classes with web browsers through Internet.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.800-807
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• 2016

We propose a fast algorithm using Extreme Contour Point (ECP) to detect the angle of rotated images, is implemented by rotation feature of one covered frame image that can be applied to correct the rotated images like in image processing for real time applications, while CORDIC is inefficient to calculate various points like high definition image since it is only possible to detect rotated angle between one point and the other point. The two advantages of this algorithm, namely compatibility to images in preprocessing by using Sobel edge process for pattern recognition. While the other one is its simplicity for rotated angle detection with cyclic shift of two $1{\times}n$ matrix set without complexity in calculation compared with CORDIC algorithm. In ECP, the edge features of the sample image of gray scale were determined using the Sobel Edge Process. Then, it was subjected to binary code conversion of 0 or 1 with circular boundary to constitute the rotation in invariant conditions. The results were extracted to extreme points of the binary image. Its components expressed not just only the features of angle ${\theta}$ but also the square of radius $r^2$ from the origin of the image. The detected angle of this algorithm is limited only to an angle below 10 degrees but it is appropriate for real time application because it can process a 200 degree with an assumption 20 frames per second. ECP algorithm has an O ($n^2$) in Big O notation that improves the execution time about 7 times the performance if CORDIC algorithm is used.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.9
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• pp.855-862
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• 2009

This paper contains the signal receiving algorithm for Galileo E5 AltBOC signal and the development of Galileo E5 signal receiving software. The software runs the process from signal acquisition to extracting measurement data to get navigation solution. It uses logged IF data file as an input. In signal acquisition stage, 1ms and delayed 1ms data are used for reducing correlation ross from secondary code and navigation bit conversion. Signal tracking stage is made of two stages which are coarse tracking and fine tracking. It is for taking advantage of AltBOC characteristic and resolving ambiguity problem due to BOC modulation. The functions of software are verified by signal processing using logged IF data from commercial GNSS simulator.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1884-1893
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• 2016

The ride-through control of a doubly-fed induction generator (DFIG) for the voltage sags on wind farms utilizing crowbar circuits by which the rotor side converter (RSC) is disabled has being reported in many literatures. An analysis and calculation of the transient current when the RSC is switched off are of significance for carrying out the low voltage ride through (LVRT) of a DFIG. The mathematical derivation is highlighted in this paper. The zero-state and zero-input responses of the transient current in the frequency domain through a Laplace transformation are investigated, and the transient components in the time domain are achieved. With the characteristics worked out from the linear resolving without modeling simplification, the selection of the resistance in the linear crowbar circuit and the value conversion from a linear circuit to a nonlinear one is proposed to setup the attenuation rate. In terms of grid code requirements, the theoretical analysis for the time constant of the transient components attenuation insures the controllability when the excitation of the RSC is resumed and it guarantees the reserved time for the response of the reactive power compensation. Simulations are executed in MATLAB/SIMPOWER and experiments are carried out to validate the theoretical analysis. They indicate that the calculation method is effective for selection of the resistance in a crowbar circuit for LVRT operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1621-1628
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• 2003

Packaging structures to block the propagation of higher­order modes in the shielded microstrip lines are designed. Packaging for microwave circuits is necessary, basically, to isolate and protect circuits from outside environments both physically and electrically. The drawback of packaging is the possibility of higher­order mode propagation, similar to waveguide modes, as the operating frequency increases. One of Possible choices for the higher­order mode suppression is to insert diaphragms to the housing structure. The shielding effects of diaphragms are analyzed using an FEM code. Several parameters such as dispersion, mode conversion, and higher­order mode transmission and reflection are analyzed. The effect of higher­order mode suppression is eminent as the depth or width of a diaphragm is increased in the air region of the microstrip line. It is shown that inductive diaphragm structure can lower ${S_21}$ for the second­order mode incidence by 30㏈, comparing with the conventional capacitive diaphragm structure. Packaging structure analyzed in this paper can be applied usefully to the design of the microwave system in a package such as transmit/receive modules.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.6
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• pp.1431-1439
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• 2017

In the security field, log analysis is important to detect malware or abnormal behavior. Recently, image visualization techniques for malware dectection becomes to a major part of security. These techniques can also be used in online games. Users can leave a game when they felt bad experience from game bot, automatic hunting programs, malicious code, etc. This churning can damage online game's profit and longevity of service if game operators cannot detect this kind of events in time. In this paper, we propose a new technique of PNG image conversion based churn prediction to improve the efficiency of data analysis for the first. By using this log compression technique, we can reduce the size of log files by 52,849 times smaller and increase the analysis speed without features analysis. Second, we apply data mining technique to predict user's churn with a real dataset from Blade & Soul developed by NCSoft. As a result, we can identify potential churners with a high accuracy of 97%.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.783-792
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• 2001

It is well known that, in the near future, the lifetime of the IPv4 address space will be limited and available 32-bit IP network addresses will not be left any more. In order to solve such IPv4 address space problem in an effective way, the transition to the new version using IPv6 architecture is inevitably required. At present, it is impossible to convert IPv4 into IPv6 at a time, since the coverage and the size of today's Internet is too huge. Therefore, the coexistence of both IPv4 and IPv6 must be arranged in a special and practical fashion for rapid conversion on the whole. IP protocol translation has been proposed to ease the translation of the Internet from IPv4 to IPv6. This paper presents the design and implementation of a transparent transition service that translates packet header as they cross between IPv4 and IPv6 networks. IPv4/IPv6 Translation Protocol is written in c source code and is tested by the local test recommended by ISO, which has the most excellent error detection function. The test was processed with a test scenario and it was found that the results were successful.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.573-580
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• 2002

Reusing IPs requires interface protocol related tasks such as writing test benches and designing interface protocol conversion circuits, e.g. wrappers for IPs. The results of those tasks usually include IPC(interface protocol component)s for the corresponding IPs, similar to bus protocol components of the bus functional models. This paper proposes a methodology for the interface circuit design using synthesizable In that can be re-used. IPC recognizes or executes transactions over the given interface ports. So we present a transaction-oriented interface protocol description language, and a method to convert the description into an IPC in synthesizable VHDL code. With experiments, we show that the interface design using IPC does not cause significant area overhead compared with the interface design without IPC. The proposed IPC-based approach can be employed to reduce the interface design time since the designers can reuse IPCs without understanding the detailed interface protocols.