• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.10-19
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• 2006

In this paper, we propose 128-bit chaotic block encryption scheme using a PLCM(Piecewise Linear Chaotic Map) having a good dynamical property. The proposed scheme has a block size of 12n-bit and a key size of 125-bit. The encrypted code is generated from the output of PLCM. We show the proposed scheme is very secure against statistical attacks and have very good avalanche effect and randomness properties.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.128-134
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• 2002

In this paper, the performance on the PN code acquisition of DS/CDMA system was analyzed using the Nakagami-m probability density function considered fading environment. The equations on detection probability, $P_D$ and false alarm probability, $P_{FA}$, decision variables affecting the PN code acquisition time were derived and proved using simulation in order to analyze the performance. In conclusion, It was necessary increasing the gain of PLL for correcting phase errors and improving the acquisition performance of PN code in apply to the rake receiver.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.8
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• pp.223-230
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• 2021

The lightweight block cipher PIPO announced at ICISC'20 has been effectively implemented by applying the bit slice technique. In this paper, we propose a parallel optimal implementation of PIPO for ARM processors. The proposed implementation enables parallel encryption of 8-plaintexts and 16-plaintexts. The implementation targets the A10x fusion processor. On the target processor, the existing reference PIPO code has performance of 34.6 cpb and 44.7 cpb in 64/128 and 64/256 standards. Among the proposed methods, the general implementation has a performance of 12.0 cpb and 15.6 cpb in the 8-plaintexts 64/128 and 64/256 standards, and 6.3 cpb and 8.1 cpb in the 16-plaintexts 64/128 and 64/256 standards. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation for each standard has about 65.3%, 66.4%, and the 16-plaintexts parallel implementation, about 81.8%, and 82.1% better performance. The register minimum alignment implementation shows performance of 8.2 cpb and 10.2 cpb in the 8-plaintexts 64/128 and 64/256 specifications, and 3.9 cpb and 4.8 cpb in the 16-plaintexts 64/128 and 64/256 specifications. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation has improved performance by about 76.3% and 77.2%, and the 16-plaintext parallel implementation is about 88.7% and 89.3% higher for each standard.

• The KIPS Transactions:PartD
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• v.9D no.5
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• pp.915-924
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• 2002

Conventional Systems for parcel sorting consist of two sequences as loading the parcel into conveyor belt system and post-code input. Using bar code information, the parcels to be recorded and managed are recognized. This paper describes a 32 $\times$ 32 sized mini-block inspection to extract bar code Region of Interest (ROI) from the line Charged Coupled Device (CCD) camera capturing image of moving parcel at 2m/sec speed. Firstly, the Min-Max distribution of the mini-block has been applied to discard the background of parcel and region of conveying belts from the image. Secondly, the diagonal inspection has been used for the extraction of letters and bar code region. Five horizontal line scanning detects the number of edges and sizes and ROI has been acquired from the detection. The wrong detected area has been deleted by the comparison of group size from labeling processes. To correct excluded bar code region in mini-block processes and for analysis of bar code information, the extracted ROI 8 boundary points and decline distribution have been used with central axis line adjustment. The ROI extraction and central axis creation have become enable within 60～80msec, and the accuracy has been accomplished over 99.44 percentage.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.32-41
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• 2010

We propose the use of multi-preambles using Gold codes and analyze its performance. The multi-preamble is a way of utilizing different codes for preambles according to operation modes or applications in a system. The receiver can be easily implemented using the maximum likelihood algorithm. The performance is robust against noise due to the good correlation characteristic of the Gold codes. We use 128-bit-long multi-preambles generated by 127 bit Gold codes in deriving the detection error probability and in verifying the validity through computer simulation. The results show that the theory and the experiment are in good agreement within the approximation error.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.57-64
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• 2000

We describe a parallel implementation for the large-eddy simulation(LES) of stratified and rotating turbulence based on MPI. The parallelization strategy is specified by eliminating the tridiagonal solver with explicit method and by domain decompositions for solving the poisson equation. In this simulation we have run on CRAY-T3E under the message passing platform MPI with a various domain decomposition and the scalability of this parallel code of LES are also presented. The result shows that we can gain up to 16 times faster speed up on 64 processors with xyz-directional domain decomposition and scalable up to $128{\times}128{\times}$ which processing time is almost similar to that of $40{\times}40{\times}40$ on a single processor machine with a sequential code.

• Transactions of the Society of Information Storage Systems
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• v.3 no.3
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• pp.126-128
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• 2007

일반적으로 주어진 하나의 H matrix 로 다수의 코드율을 가지는 코드화가 가능하다. 하지만 Low Density Parity Check(LDPC) 코드의 H matrix는 H matrix 내의 1의 개수와 위치에 따라 그 성능이 달라짐으로 해서 하나의 H matrix로 다수의 코드율을 대응하기 위한 설계 방법이 요구된다. H matrix 의 성능은 일반적으로 girth나 minimum distance에 의해 좌우되고 H matrix의 1의 위치에 따라 달라진다. 본 논문에서는 H matrix의 girth 와 minimum distance에 입각한 다수 개의 코드율이 대응 가능한 LDPC code의 H matrix 설계 방법을 제시하고자 한다. 이렇게 함으로써 하나의 H matrix로 다수의 코드율에 따른 각각의 성능을 일정 수준 이상 유지하는 multi-rate LDPC code가 가능하다.

• Korean Journal of Computational Design and Engineering
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• v.22 no.2
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• pp.118-128
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• 2017

Many countries have been developing BIM-based building code checking system and studies in the utilization of Industry Foundation Classes (IFC) in building code checking. IFC is the open standard of BIM format. Currently, there is a disadvantage that could not include all of the attribute for the regulations of each country and there is the problem with the interoperability of the different defined IFC approach between BIM software. This study focus on developing, derived object and property by comparing through domestic regulation and IFC2x3 specification provided by the buildingSMART and classified review type depending on the interoperability of derived information. According to classified review type, the IFC data structure was established and property mapping contents were developed by including BIM software compatible information and creating a type of review plan. When the developed property mapping contents are applied into BIM-based building code checking system, checking of the BIM data generated from various fields is made effective and thus improving the interoperability of information.

• Journal of Digital Convergence
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• v.14 no.10
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• pp.261-269
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• 2016

This paper aims to propose a novel technology of network convergence to provide ultra high speed internet services over CATV networks, by which a CMC(cable modem concentrator) and CM(cable modem) of 1Gbps level are designed. This technology not only lowers the production cost in comparison to the existing bonding technology with DOCSIS specification but also enables the adjustment of data speed based on the channel bandwidth. According to the experiments, when convolutional code rate with 128QAM is changed to 1/2, 2/3, 3/4 and 7/8, the data recorded the maximum transmission speed of up to 299 Mbps at the zero error rate. As the convolutional code rates with 256QAM is increased, it showed 334Mbps at the error rate of $10^{-5}$. Based on the findings of this paper, if we secure the channel bandwidth of 200MHz and adjust the modulation order of QAM and the convolution code rate depending on the channel status, we can get the transmission speed of more than 1Gbps, which is much more competitive in its function and price than the existing technology based on DOCSIS.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.34-40
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• 1999

Reed-Solomon(RS) codes have been employed to correct burst errors in applications such as CD-ROM, HDTV, ATM and digital VCRs. For the decoding RS codes, the Berlekamp-Massey algorithm, Euclidean algorithm and modified Euclidean algorithm(MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The advantages of the proposed scheme are twofold. First, The proposed architecture uses about 25% less clock cycles required in the MEA operation than[1]. Second, the number of recursive MEA cells can be reduced, when the number of clock cycles spent in the MEA operation is larger than code word length n. thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circurity for (128,124) RS code have been described and the MEA operation is verified through VHDL.