• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.667-670
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• 2003

Ni-silicide has low thermal stabiliy. This point is obstacle to apply NiSi to devices. So In this paper, we have studied for obtain thermal stability and analysis of dopant dependency of NiSi. And then we applied Ni-silicide to devices. To improvement of thermal stability, we deposit Ni70/Co10/Ni30/TiN100 to sample. Co midlayer is enhanced thermal stability of NiSi. Co/Ni/TiN, this structure show very difference between n-poly and p-poly in sheet resistance. But Ni/Co/Ni/TiN, structure show less difference. Also junction leakage is good.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.15-16
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• 2006

The thermal stability of nickel silicide with compressively and tensilely stressed nitride capping layer has been investigated in this study. The Ni (10 nm) and Ni/Co/TiN (7/3/25 nm) structures were deposited on the p-type Si substrate. The stressed capping layer was deposited using plasma enhanced chemical vapor deposition (PECVD) after silicide formation by one-step rapid thermal process (RTP) at $500^{\circ}C$ for 30 sec. It was found that the thermal stability of nickel silicide depends on the stress induced by the nitride capping layer. In the case of Ni (10 nm) structure, the high compressive sample shows the best thermal stability, whereas in the case of Ni/Co/TiN (7/3/25 nm) structure, the high compressive sample shows the worst thermal stability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.10-10
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• 2008

Silicide is inevitable for CMOSFETs to reduce RC delay by reducing the sheet resistance of gate and source/drain regions. Ni-silicide is a promising material which can be used for the 65nm CMOS technologies. Ni-silicide was proposed in order to make up for the weak points of Co-silicide and Ti-silicide, such as the high consumption of silicon and the line width limitation. Low resistivity NiSi can be formed at low temperature ($\sim500^{\circ}C$) with only one-step heat treat. Ni silicide also has less dependence of sheet resistance on line width and less consumption of silicon because of low resistivity NiSi phase. However, the low thermal stability of the Ni-silicide is a major problem for the post process implementation, such as metalization or ILD(inter layer dielectric) process, that is, it is crucial to prevent both the agglomeration of mono-silicide and its transformation into $NiSi_2$. To solve the thermal immune problem of Ni-silicide, various studies, such as capping layer and inter layer, have been worked. In this paper, the Ni-silicide utilizing Pd stacked layer (Pd/Ni/TiN) was studied for highly thermal immune nano-scale CMOSFETs technology. The proposed structure was compared with NiITiN structure and showed much better thermal stability than Ni/TiN.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.10-11
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• 2006

In this study, the Ni/Co/TiN (6/2/25 nm) structure was deposited for thermal stability estimation. Vacuum (30 mTorrs) annealing was carried out to compare with furnace annealing in nitrogen ambient. The proposed Ni/Co/TiN structure exhibited low temperature silicidation and wide range of rapid thermal process (RTP) windows. The sheet resistance was too high to measure after furnace annealing at $600^{\circ}C$ due to the thin thickness (15 nm) of the nickel silicide. However, the sheet resistance maintained stable characteristics up to $600^{\circ}C$ for 30 min after vacuum annealing. Therefore, the low resistance of thin film nickel silicide was obtained by vacuum annealing at $600^{\circ}C$.

• 한국진공학회지
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• 제7권3호
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• pp.208-213
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• 1998

최근 셀리사이드(salicide) 제조시 $COSiO_2$의 에피텍셜 성장을 돕기 위하여 Ti층을 삽 입한 Co/Ti/Si 이중층 구조의 실리사이드화가 관심을 끌고 있다. Co/Ti 이중층을 이용한 salicide 트랜지스터가 성공적으로 만들어지기 위해서는 gate 주위의 spacer oxide위에 증착 된 Co/Ti 이중층을 급속열처리할 때 Co/Ti와 $SiO_2$간의 계면에서의 상호반응에 대하여 조사 하였다. Co/Ti 이중층은 $600^{\circ}C$에서 열처리한 후 면저항이 급격하게 증가하기 시작하였는데, 이것은 Co층이 $SiO_2$와의 계면에너지를 줄이기 위하여 응집되기 때문이다. 이때 Co/Ti의 열 처리후 Ti에 의하여 $SiO_2$기판의 일부가 분해됨으로써 절연체의 Ti산화물이 형성되었으나, 이외의 도전성 반응부산물은 발견되지 않았다.

• 한국재료학회지
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• 제6권12호
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• pp.1192-1198
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• 1996

배선 재료나 salicide 트랜지스터에 적용될 것으로 기대되는 Cu 배선과 Co 단일층 및 Co/Ti 이중층을 사용하여 형성된 코발트 실리사이드간의 열적 안정성에 대하여 조사하였다. 40$0^{\circ}C$열처리후 Cu3Si 막이 CoSi2층과 Si 기판 사이에 형성되었는데, 이것은 Cu 원자의 확산에 기인한 것이다. $600^{\circ}C$에서의 열처리 후에 형성된 최종막의 구조는 각각 Cu/CoSi2/Cu3Si/Si과 TiO2/Co-Ti-Si 합금/CoSi2/Cu3Si/Si였으며, 상부에 형성된 TiO2층은 산소 오염에 의한 것으로 밝혀졌다.

• Transactions on Electrical and Electronic Materials
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• 제9권2호
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• pp.47-51
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• 2008

In this paper, thermal stability of Nickel silicide formed on p-type silicon wafer using Ni-V alloy film was studied. As compared with pure Ni, Ni-V shows better thermal stability. The addition of Vanadium suppresses the phase transition of NiSi to $NiSi_2$ effectively. Ni-V single structure shows the best thermal stability compared with the other Ni-silicide using TiN and Co/TiN capping layers. To enhance the thermal stability up to $650^{\circ}C$ and find out the optimal thickness of Ni silicide, different thickness of Ni-V was also investigated in this work.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.371-374
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• 2004

In this paper, Ni Germane-silicide formed on undoped $Si_{0.8}Ge_{0.2}$ as well as source/drain dopants doped $Si_{0.8}Ge_{0.2}$ was characterized by the four-point probe for sheet resistance. x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and field emission scanning electron microscope (FESEM). Low resistive NiSiGe is formed by one step RTP (Rapid thermal processing) with temperature range at $500{\~}700^{\circ}C$. To enhance the thermal stability of Ni Germane-silicide, Ni/Co/TiN structure with different Co concentration were studied in this work. Low sheet resistance was obtained by Ni/Co/TiN structure with high Co concentration using 2-step RTP and it almost keeps the same low sheet resistance even after furnace annealing at $650^{\circ}C$ for 30 min.

• 한국표면공학회지
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• 제35권6호
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• pp.377-382
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• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• 전자공학회논문지A
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• 제33A권7호
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• pp.134-142
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• 1996

The epi-CoSi$_{2}$ layer was formed by alloying a Co(120$\AA$)/Ti(50$\AA$) bilayer. In addition, the ultra shallow p$^{+}$n junction of which depth is about not more than 40nm at the background concentration, 10$^{18}$atoms/cm$^{3}$ could be formed by annealing (RTA-II) the ion implanted epi-silicide. When the temperature of RTA-I is as low as possible and that of RTA-II is moderate, the p$^{+}$n junction that has low leakage current and stable epi-silicide layer could be obtained. That is, when th econdition of TRA-I was 900$^{\circ}C$/20sec and that of RTA-II was 900$^{\circ}C$/10sec, the reverse leakage current was as high as 11.3$\mu$A/cm$^{2}$ at -5V. The surface of CoSi$_{2}$ appeared considerably rough. However, when the conditon of RTA-I was 800$^{\circ}C$/20sec or 700$^{\circ}C$/20sec, the leakage currents were as low as 8.3nA/cm$^{2}$ and 9.3nA/cm$^{2}$, respectively and also the surfaces appeared very uniform.