• Journal of Power Electronics
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• v.15 no.2
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• pp.327-337
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• 2015

This study discusses the design of a parallel-operated DC-DC single-ended primary-inductor converter (SEPIC) for low-voltage application and current sharing with a constant output voltage. A coupled inductor is used for parallel-connected SEPIC topology. Generally, two separate inductors require different ripple currents, but a coupled inductor has the advantage of using the same ripple current. Furthermore, tightly coupled inductors require only half of the ripple current that separate inductors use. In this proposed work, tightly coupled inductors are used. These produce an output that is more efficient than that from separate inductors. Two SEPICs are also connected in parallel using the coupled inductors with a single common controller. An analog control circuit is designed to generate pulse width modulation (PWM) signals and to fulfill the closed-loop control function. A stable output current-sharing strategy is proposed in this system. An experimental setup is developed for a 18.5 V, 60 W parallel SEPIC (PSEPIC) converter, and the results are verified. Results indicate that the PSEPIC provides good response for the variation of input voltage and sudden change in load.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.411-414
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• 2008

The study is about simulation of optical circuit for oneself performance evaluation of Fiber Optic Gyro(FOG) closed-loop controller board. The Fiber Optic Interferometer Simulator is used a digital signal processing for cosine response specificity output of fiber optic coil about input rate. Response specificity of the fiber optic coil is $Vo(t)=K3[1+\cos\{K1(Vm(t)-Vm(t-{\tau}))+K2\}]$. Also the Fiber Optic Interferometer Simulator is able to confirm a output value with K1, K2 and K3 input. The fiber Optic Interferometer Simulator is able to oneself performance evaluation without fiber optical circuit. Because, it is the very same cosine response specificity of real fiber optic coil about input rate.

• Proceedings of the KSR Conference
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• 2006.11b
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• pp.802-810
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• 2006

For a thorough train control, the precise train position detection is necessarily required. The widely used current way for train position detection is the one of using track circuits. The track circuit has a simple structure, and has a high level of reliability. However trains can be detected only on track circuits, which have to be installed on all ground sections, and much amount of cost for its installation and maintenance is needed. In addition, for the track circuit, only discontinuous position detection is possible because of the features of the closed circuit loop configuration. As the recent advances in telecommunication technologies and high-tech vehicle-based control equipments, for the train position detection, the method to detect positions directly from on trains is being studied. Vehicle-based position detection method is to estimate train positions, speed, timing data continuously, and to use them as the control information. In this paper, the features of GPS navigation and DR navigation are analyzed, and the navigation filters are designed by constructing vehicle-based train position detection method by combining GPS navigation and DR navigation for their complementary cooperation, and by using kalman filter. The position estimation performance of the proposed method is also confirmed by simulations.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.504-513
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• 2009

This paper proposes the new type LED driver modularization for illumination LED driver. The proposed LED driver circuit insulates a hot GND of AC input power and a cold GND of LED driver part by using a fly-back converter. In order to control easily the current of the LED, the fly-back converter is operated in the discontinuous mode with excellent dynamic characteristics, and the characteristics of the LED are verified after the closed loop control is performed using a KIA2431. The LED driver module allows the wide AC power input ranges and realizes the burst dimming function which directly regulates a PWM control IC. This paper describes the operation principle of the LED driver module and it is proved the usefulness through the real model with experimentation. Besides, this paper proposes the multi-channel LED driver which the miniaturized and modularized LED driver module are connected by parallel, and verified its propriety by experiments.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.3B no.1
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• pp.10-15
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• 2003

This paper presents the digital computer performance evaluations of the three-phase self-excited induction generator (SEIG) driven by the variable speed prime mover such as the wind turbine using the nodal admittance approach steady-state frequency domain analysis with the experimental results. The three-phase SEIG setup is implemented for small-scale rural renewable energy utilizations. The experimental performance results give a good agreement with those ones obtained from the digital computer simulation. Furthermore, a feedback closed-loop voltage regulation of the three-phase SEIG as a power conditioner which is driven by a variable speed prime mover employing the static VAR compensator (SVC) circuit composed of the thyristor phase controlled reactor (TCR) and the thyristor switched capacitor(TSC) is designed and considered herein for the wind-turbine driven the power conditioner. To validate the effectiveness of the SVC-based voltage regulator of the terminal voltage of the three-phase SEIG, an inductive load parameter disturbances in stand-alone are applied and characterized in this paper. In the stand-alone power utilization system, the terminal voltage response and thyristor triggering angle response of the TCR are plotted graphically. The simulation and the experimental results prove the effectiveness and validity of the proposed SVC which is controlled by the Pl controller in terms of fast response and high performances of the three-phase SEIG driven directly by the rural renewable energy utilization like a variable-speed prime mover.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1812-1819
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• 2001

In this paper, it investigated the permitted limit of the analog nonideality for the SOSOC Σ-Δ modulator design which is satisfied with 1 [MHz] signal bandwidth and 12-bit resolution in the OSR=25. Firstly, it get the SOSOC Σ-Δ modulator model and gain coefficient which is suitable in low voltage for the Σ-Δ modulator design which is satisfied with the specification in the supply voltage 3.3 [Vl. And it provided the performance prediction of the Σ-Δ modulator and the permitted limit of the nonideality by adding the performance degradation facts of the Σ-Δ modulator such as the finite gain of the amplifier, the SR, the closed-loop pole, the switch ON resistance and the capacitor mismatch to the ideal Σ-Δ modulator model. When designed the Σ-Δ modulator which is satisfied with the specification by the base above, it will be able to predict the performance of the Σ-Δ modulator and the guide for the specification of the circuit which composes the Σ-Δ modulator.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.793-799
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• 2018

The CCD camera is easily deteriorated by radiation, and an integrated camera using an image pickup tube is used in a high radiation area. We implemented a radiation camera system which is divided into a camera head using radiation-resistant electronic components and a remote control using weak radiation-resistant electronic components such as TR, IC, etc. According to the experimental results, the first damage of the electronic parts was IC for horizontal and vertical sync generation, and it was confirmed that if the radiation of $2{\times}10^5{\sim}10^6rad$ is accumulated, the normal function is lost. In addition, the signal transmission cable for remoteization has added an input/output buffer circuit and reduced the closed loop area of the shield and the cable to eliminate signal loss correction and noise. Therefore, it is expected that the maintenance cost will be greatly reduced and practical because only the camera head part can be used instead of replacing the entire system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.