• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.1-11
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• 1981

This paper proposes a method of generalizing the clocking scheme in the Switched Capacitor Filter(SCF) design using Voltage Inverter Switches (VIS's). Parallel RC and RL elements, and parallel LC resonators can be implemented by the proposed clocking schemes Applying these new elements and the generalized clocking schemes to the SCF design, the total number of required operational amplifiers and capacitors can be reduced. Experimental results of a band- stop filter and a low-pass filter using a new type grounded VIS show good agreements with t he theoretical characteristics.

• Journal of computational fluids engineering
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• v.11 no.4 s.35
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• pp.1-8
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• 2006

Clocking effects of a stator on the performance and internal flow in an UTRC 1.5 stage axial turbine are investigated using a three-dimensional unsteady flow simulation. Six relative positions of two rows of stator are investigated by positioning the second stator being clocked in a step of 1/6 pitch. The relative efficiency benefit of about 1% is obtained depending on the clocking positions. However, internal flows have some different characteristics from that in the previous study at the best and worst efficiency positions, since the first stator wake is mixed out with the rotor wake before arriving at the leading edge of the second stator. Instead of the first stator wake, it is found that the wake interaction of the first stator and rotor has a important role on a relative efficiency variation at each clocking position. The time-averaged local efficiency along the span at the maximum efficiency is more uniform than that at the minimum efficiency. That is, the spanwise efficiency distribution at the minimum efficiency has larger values in mid-span but smaller values near the hub and casing in comparison to those at the maximum efficiency. Moreover, the difference between maximum and minimum instantaneous efficiencies during one period is found to be smaller at the maximum efficiency than at the minimum efficiency.

• 유체기계공업학회:학술대회논문집
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• 2005.12a
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• pp.473-480
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• 2005

Clocking effects of a stator on the performance and internal flow in an UTRC 1.5 stage axial turbine are investigated using a three-dimensional unsteady flow simulation. Six relative positions of two rows of stator are investigated by positioning the second stator being clocked in a step of 1/6 pitch. The relative efficiency benefit of about 1% is obtained depending on the clocking positions. However, internal flows have some different characteristics from that in the previous study at the best and worst efficiency positions, since be first stator wake is mixed out with the rotor wake before arriving at the leading edge of the second stator. Instead of the first stator wake, it is found that the wake interaction of the first stator and rotor has a important role on a relative efficiency variation at each clocking position. The time-averaged local efficiency along the span at the maximum efficiency is more uniform than that at the minimum efficiency. That is, the spanwise efficiency distribution at the minimum efficiency has larger values in mid-span but smaller values near the hub and casing in comparison to those at the maximum efficiency. Moreover, the difference between maximum and minimum instantaneous efficiencies during one period is found to be smaller at the maximum efficiency than at the minimum efficiency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.303-317
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• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.33-41
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• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.1-8
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• 2005

An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.60-68
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• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.177-183
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• 2012

Cell-phones functions have advanced so rapidly and they are now called 'smart-phones.' Typical approach to optimization the performance of a smartphone is the increasing the speed of device and acquiring more free memory. In this paper, we propose relatively simple techniques that average users can apply to their devices to optimize the performance. For performance upgrade, we proposed an over-clocking technique usually used by computer manufacturers. For memory optimization, we proposed deleting unnecessary apps and replacing with better-functioning apps. We also performed experimentation by applying these techniques to a popular Android phone model and presented the results.

• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.51-56
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• 2003

We describe a charge pump circuit using VCO (voltage controlled oscillator) for storing information into local memories in neural networks. The VCO is used for adjusting the output voltage of the charge pump to the reference voltage and for reducing the fluctuation generated by the clocking scheme. The charge pump circuit is simulated by using Hynix 0.35um CMOS process parameters. The proposed charge pump operates properly regardless to the temperature and the supply voltage variation.