Design Methodology of the CMOS Current Reference for a High-Speed DRAM Clocking Circuit

초고속 DRAM의 클록발생 회로를 위한 CMOS 전류원의 설계기법

  • Published : 2000.03.01

Abstract

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

본 논문에서는 표준 메모리 공정에 구현이 가능한 CMOS 전류원의 설계 기법에 대해 논한다. 제안하는 설계기법은 자기바이어스 기법을 활용하여 공급전압의 변화에 대해 매우 좋은 특성을 갖고, 새로운 온도보상 기법을 통해 온도변화에 대한 출력전류 변이의 일차성분을 제거할 수 있으며, 칩 내의 전압잡음에 강한 새로운 전류감지 스타트업 회로를 포함한다. 이러한 CMOS 전류원의 회로설계 기법과 함께 제안된 CMOS 전류원을 초고속 DRAM의 클록 발생회로에 적용할 수 있는 방법에 대해서도 논의한다. 본 논문에서 제안된 CMOS 전류원의 설계기법은 해석적인 방법과 함께 회로 시뮬레이션을 통해 그 유용성을 입증한다.

Keywords

References

  1. Thomas H. Lee et al., 'A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,' IEEE J. Solid-State Circuits, vol. 29, no. 12, pp.1491-1496, Dec. 1994 https://doi.org/10.1109/4.340422
  2. Yasuhiro Takai et aI., 'A 250Mb/s pin 1Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shares Redundancy Scheme', ISSCC Dig. Tech Papers, pp. 418-419 Feb. 1999
  3. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and Winston, New Yark, 1987
  4. Daejeong Kim, Sung Ho Cho, 'CMOS Current Source Circuit,' United States Patent no. 5,744,999 Apr. 28, 1998
  5. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, New York, 1993
  6. Dong-Sun Min et aI., 'Temperature-Compensation Circuit Techniques for High-Density CMOS DRAM's,' IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 626-631, Apr. 1992 https://doi.org/10.1109/4.126553
  7. Hironori Banda et aI., 'A CMOS Bandgap Reference Circuit with Sub-1- V Operation,' IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670-674, May 1999 https://doi.org/10.1109/4.760378
  8. Ho-Jun Song et aI., 'A Temperature-Stabilized SOl Voltage Reference Based on Threshold Voltage Difference Between Enhancement and Depletion NMOSFET's,' IEEE J. Solid-State Circuits, vol. 28, no. 6, pp. 671-677, Jun. 1993