• Journal of Positioning, Navigation, and Timing
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• v.6 no.3
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• pp.125-133
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• 2017

Time comparison is necessary for the verification and synchronization of the clock. Two-way satellite time and frequency (TWSTFT) is a method for time comparison over long distances. This method includes errors such as atmospheric effects, satellite motion, and environmental conditions. Ionospheric delay is one of the significant time comparison error in case of the carrier-phase TWSTFT (TWCP). Global Ionosphere Map (GIM) from Center for Orbit Determination in Europe (CODE) is used to compare with Bernese. Thin shell model of the ionosphere is used for the calculation of the Ionosphere Pierce Point (IPP) between stations and a GEO satellite. Korea Research Institute of Standards and Science (KRISS) and Koganei (KGNI) stations are used, and the analysis is conducted at 29 January 2017. Vertical Total Electron Content (VTEC) which is generated by Bernese at the latitude and longitude of the receiver by processing a Receiver Independent Exchange (RINEX) observation file that is generated from the receiver has demonstrated adequacy by showing similar variation trends with the CODE GIM. Bernese also has showed the capability to produce high resolution IONosphere map EXchange (IONEX) data compared to the CODE GIM. At each station IPP, VTEC difference in two stations showed absolute maximum 3.3 and 2.3 Total Electron Content Unit (TECU) in Bernese and GIM, respectively. The ionospheric delay of the TWCP has showed maximum 5.69 and 2.54 ps from Bernese and CODE GIM, respectively. Bernese could correct up to 6.29 ps in ionospheric delay rather than using CODE GIM. The peak-to-peak value of the ionospheric delay for TWCP in Bernese is about 10 ps, and this has to be eliminated to get high precision TWCP results. The $10^{-16}$ level uncertainty of atomic clock corresponds to 10 ps for 1 day averaging time, so time synchronization performance needs less than 10 ps. Current time synchronization of a satellite and ground station is about 2 ns level, but the smaller required performance, like less than 1 ns, the better. In this perspective, since the ionospheric delay could exceed over 100 ps in a long baseline different from this short baseline case, the elimination of the ionospheric delay is thought to be important for more high precision time synchronization of a satellite and ground station. This paper showed detailed method how to eliminate ionospheric delay for TWCP, and a specific case is applied by using this technique. Anyone could apply this method to establish high precision TWCP capability, and it is possible to use other software such as GIPSYOASIS and GPSTk. This TWCP could be applied in the high precision atomic clocks and used in the ground stations of the future domestic satellite navigation system.

• Journal of the Korean Institute of Navigation
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• v.14 no.2
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• pp.1-14
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• 1990

The Radio Navigation System(R. N. S.) has been progressed consistantly with the development of electric-electronic engineering techniques since the R. D. E had been developed in 1910. The R. N. S. mostly depends on either Hyperbolic Navigation System(H. N. S.) or Spherical Navigation System(S. N. S.) in the ocean, and on Rectangular Navigation System (R. N. S.) in the air near the airport or an a combinations of the above systems in both area. Another effective R. N. S may be the Ellipse-Hyperbola Navigation System(E-H N. S.), which is proposed and named such in this paper. The equations calculating GDOP are derived and the GDOP values are calculated in the case of H. N. S., S. N. S, and E-H. N. S., respectively, for the specified case that four transmitting stations are arranged on the apex of a square, Then the GDOP diagrams of above navigation systems are presented for qualitative comparison in this paper. To measure the distances from the receiver to the stations in S. N. S., and/or the sum of distances to two stations in E-H N. S., the time synchronization between the transmitter clocks and the receiver clock is a major premise. The author has proposed the algorithm for getting this synchronmization utilizing the by S. N. S. or E-H N. S while GDOPs of those are relatively good. Even though clock synchronization error is a voidable due to the fix error used, the simulated results shows that the position accuracy of S. N. S. and E-H N. S. by the proposed method is far upgraded compared with that determined by H. N. S. directly, as far as the outer region of transmitter arrangement is concerned.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.7
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• pp.545-551
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• 2013

Timing recovery loop composed of the Timing Error Detector(TED), loop filter and resampler is widely used for the timing synchronization in MQASK receivers. Since TED is sensitive to the delay between the symbol period of the signal and sampling period, the output is averaged out when the symbol rate and sampling rate are quite different the recovery loop cannot work at all. This paper presents a sampling frequency discriminator (SRD), which detects the frequency offset of the sampling clock to the symbol clock of the MQASK data transmitted. Employing the SRD, the closed loop timing recovery scheme performs the frequency-aided timing acquisition and achieve the synchronization at extremely high sampling frequency offset, which can be used in variable symbol rate MQASK receivers.

• Journal of IKEEE
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• v.23 no.3
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• pp.1092-1095
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• 2019

In this paper, we propose the development of an embedded board for construction of smart factory. The proposed embedded board for construction of smart factory consists of main module, ADC module, I/O module. Main module is a main calculating device which includes communication pard that allows interface with external device with using industrial protocol and is ported operating system makes board operating into. ADC module takes part in transferring digital signal has converted from electrical signal to the main module from the external sensor which is installed on the field. I/O module is an input and output module which transfers to the main module about a status, alarm, command signal of field device and it has a function that blocks external noises from field device with isolation circuit into it. In order to evaluate the performance of the proposed embedded board for construction of smart factory, it has been tested by an authorized testing institute. As a result, quantity of interacting protocol was 5, speed of hardware clock synchronization was under 10us and operating time of battery without source power was over 8 hours. It produced the same result as the world's highest level.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.469-478
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• 2001

It is difficult to test a distributed system because of the task of controlling concurrent events,. Existing works do not propose the test sequence generation algorithm in a formal way and the amount of message is large due to synchronization. In this paper, we propose a formal test sequence generation algorithm using logical clock to control concurrent events. It can solve the control-observation problem and makes the test results reproducible. It also provides a generic solution such that the algorithm can be used for any possible communication paradigm. In distributed test, the number of channels among the testers increases non-linearly with the number of distributed objects. We propose a new remote test architecture for solving this problem. SDL Tool is used to verify the correctness of the proposed algorithm and it is applied to the message exchange for the establishment of Q.2971 point-to-multipoint call/connection as a case study.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.10
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• pp.373-380
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• 2022

This paper presents a deep learning based group synchronization that supports networked immersive interactions between remote users. The goal of group synchronization is to enable all participants to synchronously interact with others for increasing user presence Most previous methods focus on NTP-based clock synchronization to enhance time accuracy. Moving average filters are used to control media playout time on the synchronization server. As an example, the exponentially weighted moving average(EWMA) would be able to track and estimate accurate playout time if the changes in input data are not significant. However it needs more time to be stable for any given change over time due to codec and system loads or fluctuations in network status. To tackle this problem, this work proposes the Deep Group Synchronization(DeepGroupSync), a group synchronization based on deep learning that models important features from the data. This model consists of two Gated Recurrent Unit(GRU) layers and one fully-connected layer, which predicts an optimal playout time by utilizing the sequential playout delays. The experiments are conducted with an existing method that uses the EWMA and the proposed method that uses the DeepGroupSync. The results show that the proposed method are more robust against unpredictable or rapid network condition changes than the existing method.

• Journal of Satellite, Information and Communications
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• v.4 no.2
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• pp.39-45
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• 2009

This paper proposes the specific code synchronization technique for DS-SS(Direct Sequence-Spread Spectrum transmission in the DVB-RCS +M standard. DS-SS is better than multi-carrier transmission method under nonlinear channel but imposes a long acquisition time. To improve the synchronization aspect, the robust correlation structure is introduced for acquisition and the nonlinear delay lock loop is done for tracking. MAT(Mean Acquisition Time) performances is shown to validate its superiority. In addition, code tracking and jitter performances are done when code tracking algorithm based on 2 oversamples which is not influenced by sampling clock timing offset and carrier freq. offset is used.

• The Journal of the Korea Contents Association
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• v.9 no.7
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• pp.76-85
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• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area network. The node works on its local clock and the frequency differences of nodes have serious affects on ranging algorithms estimating locations of mobile nodes. The low rate UWB, IEEE802.15.4a, describes asynchronous two way ranging methods such as TWR and SDS-TWR working without any additional network synchronization, but the algorithms can not eliminate the effect of clock frequency differences. Therefore, the mechanisms to characterize the crystal difference is essential in typical UWB PHY implementations. In high rate UWB, characterizing of crystal offset with tracking loop is not required. But, detection of the clock frequency offset between the local clock and remote clock can be performed if there is little noise induced jitter. In this paper, we complete related ranging equations of high rate UWB based on TWR with relative frequency offset, and analyze a residual error in the ideal equations. We also evaluate the performance of the relative frequency offset algorithm by simulation and analyze the ranging errors according to the number of TWR to compensate coarse clock resolution. The results show that the relative frequency offset compensation and many times of TWR enhance the performance to converge to a limited ranging errors even with coarse clock resolutions.