• 한국농공학회지
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• 제41권2호
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• pp.37-43
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• 1999

This study was conducted to develop the simple and convenient irrigation control model which can maintain the appropriate rates of irrigation and drainage of nutrient solution according to the enviornmental conditions and growth stages in soilless culture of cucumber. In order to obtain fundamental data for development of the model, investigation of the actual state of soilless culture practices was carried out. Most irrigatioin systems of soillness culture were controlled by the time colock. Evapotranspiration of cucumber in soilness culture was investigated and correlations with environmental conditions were analyzed , and its estimating model was developed. In order to develop the irrigation system which can control the amount of nutrient solution applied according to seasons, weather conditions, and growth stages, a irrigation clock control was developed. Applicability of the model was tested by simulation. Drainage rates of nutrient solution controlled by conventional time clock, integrated solar radiation, and the developed model were 61% , 20%, and 32% , respectively in cucumber perlite culture.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.381-384
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• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

• 반도체디스플레이기술학회지
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• 제22권1호
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• 한국콘텐츠학회논문지
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• 제12권5호
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• pp.62-69
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• 2012

새롭게 등장한 미디어아트는 디지털미디어 시대에 맞추어 새롭고 다양한 표현방법으로 발전하고 있다. 전통예술과 다르게 관객이 적극적 주체가 되어 작품에 참여하고 상호작용하게 되면서 관객과의 소통이 크게 중요해졌다. 이러한 디지털 예술작품들이 이제는 단순히 갤러리에서만 구현되는 것이 아니라 일상생활에서 손쉽게 접하는 장소 및 물품에서도 그 모습을 볼 수가 있다. 이러한 작품들은 더욱 상호작용을 함으로써 미디어아트의 대중적 접근을 쉽게 만들고 있다. 이에 본 논문을 통해 파티클 시스템을 이용한 실시간 멀티미디어 시계 작품을 구성하는 연구를 하였다. 시간은 오랜 기간 동안 전통예술 영역에서 중요한 테마로 활용되어왔으며 다양하게 표현되고 있다. 시간의 연속성과 그에 따른 존재의 가치를 테크놀로지 기술을 바탕으로 표현하기 위하여 시계라는 대중적 매체를 활용하고 사용성과 관객의 상호작용에 의한 감성적 만족을 함께 제공할 수 있는 작품을 제안한다.

• 한국통신학회논문지
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• 제22권8호
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• pp.1765-1773
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• 1997

PLL을 사용하는 통신 시스템에서는 선로 잡음에 의해서 사이클 슬립 현상이 발생 할 수 있다. 이 사이클 슬립 현상이 동기식 스트림 암호 통신 시스템에 발생하면 난수 동기 이탈 현상을 발생시켜 통신을 할 수 없게 된다. 이러한 난수 동기 이탈의 위험성을 줄이기 위하여 연속 재동기 방식을 사용하지만 이에 따른 문제점이 있다. 본 논문에서는 수신 클럭 복원시에 사용되는 수신 클럭 보상 알고리즘을 연속 재동기 방식에 적용하여 기존의 연속 재동기 방식의 문제점을 해결하는 방법을 제안하였다. 즉, 정해진 기준 시간 동안에 실제 수신 클럭 펄스 수를 계수하여 얻은 계수치와 동일 시간 동안에 사이클 슬립이 발생하지 않은 정상 상태에서의 수신 클럭 펄스 수인 정상치가 일치하지 않으면 사이클 슬럽이 발생된 것으로 판단하여 훼손된 수신 클럭을 사이클 스립의 발생 형태에 따라 클럭 펄스를 더해주거나 빼주는 방법을 연속 재동기 방식과 같이 사용하였다. 제안된 방법을 절대 클럭 동기를 요구하는 동기식 스트림 암호 통신 시스템에서 시험한 결과 기존의 연속 재동기 방법에 비하여 재동기 시간을 최대 20배까지 단축시켰는데 그것은 전송 데이터 량을 17.8% 감축하는 효과와 동일하다.

• Journal of Positioning, Navigation, and Timing
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• 제12권3호
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• pp.215-228
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• 2023

The State Space Representation (SSR) method provides individual corrections for each Global Navigation Satellite System (GNSS) error components. This method can lead to less bandwidth for transmission and allows selective use of each correction. Precise Point Positioning (PPP) - Real-Time Kinematic (RTK) is one of the carrier-based precise positioning techniques using SSR correction. This technique enables high-precision positioning with a fast convergence time by providing atmospheric correction as well as satellite orbit and clock correction. Currently, the positioning service that supports PPP-RTK technology is the Quazi-Zenith Satellite System Centimeter Level Augmentation System (QZSS CLAS) in Japan. A system that provides correction for each GNSS error component, such as QZSS CLAS, requires monitoring of each error component to provide reliable correction and integrity information to the user. In this study, we conducted an analysis of the performance of residual error bounding for each error component. To assess this performance, we utilized the correction and quality indicators provided by QZSS CLAS. Performance analyses included the range domain, dispersive part, non-dispersive part, and satellite orbit/clock part. The residual root mean square (RMS) of CLAS correction for the range domain approximated 0.0369 m, and the residual RMS for both dispersive and non-dispersive components is around 0.0363 m. It has also been confirmed that the residual errors are properly bounded by the integrity parameters. However, the satellite orbit and clock part have a larger residual of about 0.6508 m, and it was confirmed that this residual was not bounded by the integrity parameters. Users who rely solely on satellite orbit and clock correction, particularly maritime users, thus should exercise caution when utilizing QZSS CLAS.

• Journal of information and communication convergence engineering
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• 제11권3호
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• pp.190-198
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• 2013

Recently, one of the most vital advancement in the field of finance is high-performance trading using field-programmable gate array (FPGA). The objective of this paper is to design high-performance Black Scholes option trading system on an FPGA. We implemented an efficient Black Scholes Call Option System IP on an FPGA. The IP may perform 180 million transactions per second after initial latency of 208 clock cycles. The implementation requires the 64-bit IEEE double-precision floatingpoint adder, multiplier, exponent, logarithm, division, and square root IPs. Our experimental results show that the design is highly efficient in terms of frequency and resource utilization, with the maximum frequency of 179 MHz on Altera Stratix V.

• 제어로봇시스템학회논문지
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• 제6권6호
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• pp.478-485
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• 2000

A discrete event systems (DES) is a physical system that is discrete in time and state space, asynchronous (event rather than clock-driven), and in some sense generative(or nondeterministic). This paper presents the design of fifteen modular supervisors to control an experimental CIM testbed. These supervisors are nonblocking, controllable and nonconflicting. After verification of the supervisors by simulation, the supervisors for AGV system have been implemented to demonstrate their efficacy.

• 전자공학회논문지C
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• 제35C권1호
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• pp.10-14
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• 1998

In this paper a double edge triggered (DET) filp-flop is proposed which changes its output state at both the positive and the negative edge transitions of the triggering input. DET filp-flop has advantages in terms of speed and power dissipation over single edge triggered (SET) filp-flop has proposed DET flip-flop needs only 12 MOS transistors and can operate at clock speed of 500 MHz. Also, the power dissipation has decreased about 33% in comparison to SET flip-flop.