• Dementia and Neurocognitive Disorders
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• v.17 no.3
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• pp.100-109
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• 2018

Background and Purpose: Although the clock drawing test (CDT) is a widely used cognitive screening instrument, there have been inconsistent findings regarding its utility with various scoring systems in patients with mild cognitive impairment (MCI) or dementia. The present study aimed to identify whether patients with MCI or dementia exhibited impairment on the CDT using three different scoring systems, and to determine which scoring system is more useful for detecting MCI and mild dementia. Methods: Patients with amnestic mild cognitive impairment (aMCI), vascular mild cognitive impairment (VaMCI), mild Alzheimer's disease (AD), mild vascular dementia (VaD), and cognitively normal older adults (CN) were included. All participants were administered the CDT, the Korean-Mini Mental State Examination (K-MMSE), and the Clinical Dementia Rating scale. The CDT was scored using the 3-, 5-, and 15-point scoring systems. Results: On all three scoring systems, all patient groups demonstrated significantly lower scores than the CN. However, while there were no significant differences among patients with aMCI, VaMCI, and AD, those with VaD exhibited the lowest scores. Area under the Receiver Operating Characteristic curves revealed that the three CDT scoring systems were comparable with the K-MMSE in differentiating aMCI, VaMCI, and VaD from CN. In differentiating AD from CN, however, the CDT using the 15-point scoring system demonstrated the most comparable discriminability with K-MMSE. Conclusions: The results demonstrated that the CDT is a useful cognitive screening tool that is comparable with the Mini-Mental State Examination, and that simple CDT scoring systems are sufficient for differentiating patients with MCI and mild dementia from CN.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.193-196
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• 2001

For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.77-84
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• 1998

A voltage controlled chaotic circuit has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated chaotic circuit consist of sample and hold circuits, op-amps, nonlinear function generator and two phase clock generator. The test results of the chaotic circuit show that periodic state, quasi-periodic state and chaotic state can be obtained according to the input control voltage with the ${\pm}$2.5V power supply and clock rate of 20kHz. In addition, two dimensional chaotic patterns have been observed by connecting this circuit in parallel or series

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.71-77
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• 2020

In this paper, we propose a method in which PingPong256 combines LFSR and variable clock to generate an irregular PRNG and use it for image encryption. PingPong256 is guaranteed an extended period based on the two LFSRs, and the variable clock is a structure that outputs the result of operating a predetermined clock in one operation by referring to the state of the different LFSR. A variable clock is characterized by the difficulty of predicting the output at any time because the choice increases with time. PingPong256 combines the advantages of LFSR and variable clock, the convenience of hardware and software implementation, and the benefits of sensitivity and irregular periods. Also, the statistical safety was verified using the NIST SP800-22, the safety of the proposed method, and the sensitivity of the image change was tested using NPCR and UACI.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.52-58
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• 2001

This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.

• Journal of Communications and Networks
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• v.6 no.2
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• pp.93-105
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• 2004

This paper discusses cyclostationary interference suppression for multiuser wired communication systems. Crosstalk interference from digital signals in multipair cables has been shown to be cyclostationary. Many crosstalk equalization or suppression techniques have been proposed which make implicit use of the cyclostationarity of the crosstalk interferer. In this paper, the convergence and steady-state behaviors of a fractionally spaced equalizer (FSE) in the presence of multiple cyclostationary crosstalk interference are thoroughly analyzed by using the equalizer's eigenstructure. The eigenvalues with multiple cyclostationary interference depend upon the folded signal and interferer power spectra, the cross power spectrum between the signal and the interferer, and tile cross power spectrum between the interferers, which results in significantly different initial convergence and steady-state behaviors as compared to the stationary noise case. The performance of the equalizer varies depending on the relative clock phase of the symbol clocks used by the signal and multiple interferers. Measued characteristics as well as analytical model of NEXT/FEXT channel are used to compute the optimum and worst relative clock phases among the signal and multiple interferers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1440-1446
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• 2008

In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1002-1005
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• 2015

Mobile operating systems have been typically classified into Apple and Android. Samsung showed its own new mobile OS developing Tizen based on Linux kernel. Mobile operating system has developed a technology using low-power by itself because of the limitation of capacity of battery, a feature of mobile. Samsung Tizen OS has a low-power technology called Power Manager controling LCD states as users'inputs or time-out events occur. However, if users'input occurs frequently, energy consumption jumped before-and-after users'input because CPU clock is increased rapidly due to overhead increase for frequent LCD state changes. This paper proposes a mechanism to reduce the overhead for LCD state changes, when user's input is frequent, by adding a new state to the Power Manager the current Tizen OS is using. We have implemented the proposed mechanism at Tizen phone kernel layer in this paper and experimented the mechanism according to users' LCD touch inputs. The experiment shows that it is possible to decrease energy by reducing the CPU clock increase according to the frequent user's inputs.