• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.903-906
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• 2003

In this paper, we proposed high slew-rate and low-power OP-AMP of the data driver for TFT-LCDs. Proposed OP-AMP contains newly developed rail-to-rail class-AB input circuit which enables the low-quiescent current and high slew-rate OP-AMP. The slew-rate and the quiescent current of the proposed OP-AMP are 31.2V/$\mu$sec and 5$\mu$A, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.61-66
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• 2007

A gain enhancement rail-to-rail buffer amplifier for liquid crystal display (LCD) source driver is proposed. An op-amp with extremely high gain is needed to decrease the offset voltage of the buffer amplifier. Cascoded floating current source and class-AB control block in the op-amp achieve a high voltage gain by reducing the channel length modulation effect in high voltage technologies. HSPICE simulation in $1\;{\mu}V$ 15 V CMOS process demonstrates that voltage gain is increased by 30 dB. The offset voltage is improved from 6.84 mV to $400\;{\mu}V$. Proposed op-amp is fabricated in an LCD source driver IC and overall system offset voltage is decreased by 2 mV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.637-638
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• 2006

A novel 1.2V class-AB output stage for the SW-OpAmp technique was presented. By using current mirrors and simple current extraction circuits, the proposed circuit boosts DM signal currents while eliminates CM ones to perform class-AB operation. Hspice simulation results verify the versatility of the proposed circuit technique.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.1-6
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• 2001

In this paper, a 1.5 V high-gain high-frequency CMOS complementary operational amplifier is presented. The input stage of op-amp is designed for supporting the constant transconductance on the Input stage by consisting of the parallel-connected rail-to-rail complementary differential pairs. And consisting of the class-AB rail-to-rail output stage using the concept of elementary shunt stage and the grounded-gate cascode compensation technique for improving the low PSRR which was a disadvantage in the general CMOS complementary input stage, the load dependence of open loop gain and the stability of op- amp on the output load are improved, and the high-gain high-frequency operation can be achieved. The designed op-amp operates perfectly on the complementary mode with the 180° phase conversion for a 1.5 V supply voltage, and shows the DC open loop gain of 84 dB, the phase margin of 65°, and the unity gain frequency of 20 MHz. In addition, the amplifier shows the 0.1 % settling time of .179 ㎲ for the positive step and 0.154 ㎲ for the negative step on the 100 mV small-signal step, respectively, and shows the total power dissipation of 8.93 mW.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1117-1120
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• 2003

In this paper, a 1.5V CMOS high frequency operational amplifier for high frequency signal processing systems is presented. For obtaining the high gain and the high unity gain frequency with the 1.5V supply voltage, the op-amp is designed with simple two stages which are consisting of the rail-to-rail differential input stage and the class-AB output stage. The designed op-amp operates with the 1.5V supply voltage, and shows well the push-pull class-AB operation. The simulation results show the DC open loop gain of 77dB and the unity gain frequency of 100MHz for the 1㏁ ┃ 10pF load. When the resistive load R$_1$. is varied from 1㏁ to 1 ㏀, the DC open loop gain decreases by only 4dB.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.530-532
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• 2002

We have developed a low-power, high slew-rate OP-AMP for large size and high resolution TFT-LCDs which have 8${\mu}$A quiescent current with settling time less than 6${\mu}$sec. The proposed OP-AMP contains newly developed the driving circuit of class-AB output stage which can achieve a low quiescent current less than 8${\mu}$A and a slew-rate higher than 3.14V/${\mu}$sec.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.27-30
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• 2003

Wireless power transmission system is one of the very interesting field not only in a technical and economical point of view but also that people are still trying to realize lossless power transmission. This paper has a purpose on the efficient power transmission at the passive type ICcard by using wireless power transmission system. The most difficult but important part of the passive type RF-ID system is building the system that supplies power from Reader-antenna to IDcard-antenna. To check what is the most efficient way to deliver power depending on what kind of specifications of the power-amp in reader, antenna and antenna in IDcard is for operating IDcard circuit efficiently receiving the power from reader-antenna. For this, we used 125kHz sinewave for RF signal as a basic specification, power-amp : OP-Amp for amplifying signal and AB Class push-pull power-amp for amplifying power, loop type antenna.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1120-1122
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• 1995

This paper presents a 2-stage, simple, power-efficient 3V CMOS operational amplifier and its equation based design optimization. Because of its simple structure, it is very suitable as a VLSI library cell in analog/digital mixed-mode systems. The op-amp, which contains a constant-$g_m$ rail-to-rail input stage and a simple feedforward class-AB rail-to-rail output stage, is analyzed and the results are presented in the form of design equations and procedures, which provide an insight into the trade-offs among performance requirements. The results of SPICE simulations are shown to agree very welt with the use of design equations.