• 전자공학회논문지C
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• 제35C권7호
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• pp.11-19
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• 1998

A signal line potential variation due to the delta-I noise was physically investigated in CMOS integrated circuits. An equivalent circuit for the noise analysis was presented. The signal line was modeled as segmented RC-lumped circuits with the ground noise. Then the equivalent circuit was mathematically analyzed. Therebvy a new signal line potential variation model due to the switching mosie was developed. Th emodel was verified with 0.35.mu.m CMOS deivce model parameters. The model has an excellent agreement with HSPICE simulation. Thus the proposed model can be dirctly employed in the industry to design the high-performance integrted circuit design as well as integrated circuit package design.

• 전자공학회논문지A
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• 제30A권9호
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• 전자공학회논문지A
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• 제32A권12호
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.376-378
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• 1995

A method is presented for the design and fabrication of the temperature compensation circuits on the Clark electrodes for measuring the dissolved oxygen(DO) concentration. The discussion includes a method of the sensor interface circuits for the DO sensor. Typical polarograms for the DO probes under test using this sensor circuits are presented. High accuracy over 99 % of the I to V conversion using the proposed circuit is verified. Temperature dependence for the test DO probe is well compensated automatically using the thermistor($2k\Omega,\;25^{\circ}C$) in series with correction resistor in the feedback loop of the op-amp circuit in the temperature range of the 0-50$^{\circ}C$.

• 한국응용과학기술학회지
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• 제32권4호
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• pp.724-730
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• 2015

For ex-vivo diabetic control, the voltammetric diagnosis of glucose (GU) was conducted with a modified carbon nanotube paste electrode, using handheld analytical circuits. The optimum analytical conditions were attained within the 0.5-4.0 ug/L working range and at the 0.06 ug/L detection limit, which system was interfaced to the feedback circuits and was applied to human urine for diabetic-patient diagnosis. It can be used for ex-vivo flow control analysis, vascular flow detection and other medicinal assays. The equations of the patients' urine are y=36.65x+12.13 and $R^2=0.987$, those of the healthy person of y= 2.5x+10.9 and $R^2=0.928$ (patients: 118 ug/L; healthy person: 12.34 ug/L).

• 한국응용과학기술학회지
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• 제31권2호
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• pp.210-217
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• 2014

For ex-vivo diabetic control, the voltammetric diagnosis of glucose (GU) was conducted with a modified carbon nanotube paste electrode, using handheld analytical circuits. The optimum analytical conditions were attained within the 0.5-4.0 ug/L working range and at the 0.06 ug/L detection limit, which system was interfaced to the feedback circuits and was applied to human urine for diabetic-patient diagnosis. It can be used for ex-vivo flow control analysis, vascular flow detection, and other medicinal assays.

• Journal of Advanced Marine Engineering and Technology
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• 제33권5호
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• pp.756-761
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• 2009

In this paper, a X band voltage controlled oscillator is proposed. The oscillator uses a transistor as an oscillating element and its oscillating frequencies are controlled by the tuning voltage of varactor diode. Using the circuit simulation tools, the matching circuits between the transistor and varactor diode, its input and output matching circuits, and a feedback circuits are designed. The measured results of the fabricated oscillator show that its oscillation frequencies are from 10.50GHz to 10.88GHz according to the turning voltages of 1V to 18V, its output power levels are about 4.3dBm, and its phase noise is around -43.5dBc/Hz at 100kHz offset frequency of 10.5GHz.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.45-49
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• 1998

In this paper, the direct thrust control of PWM Inverter-fed Single-sided Linear Induction Motor (hereinafter referred to as "SLIM") is achieved with Space Vector control and PI control. The trembling of air gap length which is occured between the primary winding core and the secondaty structure of the SLIM must be minimized in order to get quick response characteristic. First, voltage equations of SLIM are shown on the suitable d-q axis equivalent circuits which analyze characteristics of the thrust and the normal force. Also, modeling and analysis of the d-q axis equivalent circuits are able to make robust transient thrust from the current regulation in the equivalent circuits. These results exemplified the direct drive of SLIM with the reference speed and thrust were verified by the experiments.periments.