• Journal of Korean Medical classics
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• v.31 no.1
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• pp.79-93
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• 2018

Objectives : The climate changes in the natural realm displays pheonomena of excess and deficiency due to the principle of Yiyinyiyangzhiweidao. Here, overabundant qi arises due to the works of multiplication and insultation. When this overabundant qi is in force, the retaliating qi appears without fail to create a parallel. This is the Autonomous Equilibrium Mechanism found in the natural world. Studying this mechanism is deeply significant in understanding the mechanisms of diseases. Methods : The paper is written by reviewing the texts found in Huangdineijing's Chapters of Yunqi, which are $Q{\grave{i}}jiaobiandalun$, Wuchangzhengdalun, $Liuyuanzhengj{\grave{i}}dalun$, Zhizhenyaodalun, and Suwenliuqixuanzhumiyu. Results & Conclusions : The overabundance and retaliation in Five Circuits take the form of the restrained child of the Five Circuits takes revenge on the overabundant qi on behalf of his mother. The overabundance and retaliation in Six Qi take the form of rapid healing of Benqi which was in stagnation. Traditionally, overabundant qi is the only one in existence when the Five Circuits are in excess and the year of Hai yin wu wei you xu's regular transformation. During this time, retaliating qi does not exist. When Five Circuits are in deficiency and in the year of Si shen zi chou mao chen's pattern transformation, both the overabundant and deficiency qis exist. However, regardless of regular transformation or pattern transformation, overabundant qi and retaliating qi cannot exist at the same time. This seems to be the rational conclusion. There are some regulations that overabundance and retaliation follow. First, the strong and weak, and number of days coincide. Second, overabundance qi appear during the first half of the period when the qi of controling heaven is in place. During the later half of the period when the qi of terrestrial effect is in force, retaliation qi is the one that appears. Third, overabundance and retaliation does not end with one time. Rather, they will continue to repeat appearance and disappearance without any set pattern. Fourth, the overabundance and retaliation of the guest qi and dominant qi only has overabundance and no retaliation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.420-424
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• 1999

In this paper, an optical switching circuit and several types of all-optical transmitter/receiver circuits which are configured with photodiodes, multiple quantum-well(MQW) optical modulators, and field-effect transistors(FETs) were simulated using PSPICE and their results of these are examined and discussed. 20 $\mu\textrm{m}$ ${\times}$ 20 $\mu\textrm{m}$ of window size was used for the optical modulators and 100 $\mu\textrm{m}$ wide FETs with the transconductance value of 55 mS/mm were used for the simulations. Simulation results clearly show that in order for the high speed operation of the all-optical circuits, the size of each device should be minimized to reduce the parasitic capacitance, the circuits should be designed to operate at the wavelength where the resposivity of photodiodes becomes the maximum peak, and the use of short, high-intensity input optical signal beams is very advantageous.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.34-41
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• 1999

In this paper, hot carrier induced performance degradation of peripheral circuits in memory devices such as static type imput buffer, latch type imput buffer and sense amplifier circuit has been measured and analyzed. The used design and fabrication of the peripheral circuits were $0.8 {\mu}m$ standard CMOS process. The analysis method is to find out which device is most significantly degraded in test circuits by using spice simulation, and then to characterize the correlation between device and circuit performance degradation. From the result of the performance degradation of static type input buffer, the trip point was increased due to the transconductance degradation of NMOS. In the case of latch type input buffer, there was a time delay due to the transconductance degradation of NMOS device. Finally, hot carrier induced the decrease of half-Vcc voltage and the increased of sensing voltage in sense amplifier circuits have been measured.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2528-2535
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• 2000

Technology mapping is a part of VLSI CAD system, where circuits in logical level are mapped into circuits in physical level. The performance of technology mapping system is evaluatecJ by the delay and area of the resulting circuits. In the sequential circuits, the delay of the circuit is decided by the maximal delay between registers. In this work, we introduce an FPGA mapping algorithm improved by retiming technique used in constructive level and iterative level, and by fuzzy logic technique. Initial circuit is mapped into an FPGA circuit by constructive manner and improved by iterative retiming. Criteria given to the initial circuit are structured hierarchically by decision-making functions of fuzzy logic. The proposed system shows better results than previous systems by the experiments with MCNC benchmarkers.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.37-41
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• 2018

This paper presents the integrated fluorescent oxygen sensor probe module based on planner lightwave circuits using UV imprint lithography. The oxygen sensor system is consisted of the optical source part, optical detector part and optical sensing probe part to be composed of the planner lightwave circuit and oxygen sensitive thin film layer. Firstly, we optimally designed the planner lightwave circuit with asymmetric $1{\times}2$ beam splitter using beam propagation method. Then, we fabricated the planner lightwave circuits using UV imprint lithography process. This planner lightwave circuits transmitted the optical power with 76% efficiency and the fluorescence signal with 70% efficiency. The oxygen sensitive thin film layer is coated on the end face of planner lightwave circuit. The oxygen sensor system using this sensor probe module with planner lightwave circuit could measure the concentration with 0.3% resolution from 0% to 20% gas range. This optical oxygen sensor probe module make it possible to compact, simple and cheap measurement system.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.558-563
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• 2021

Quantum-Dot Cellular Automata is a next-generation nanocircular design technology that is drawing attention from many research organizations not only because it is possible to design efficient circuits by overcoming the physical size limitations of existing CMOS circuits, but also because of its energy-efficient features. In this paper, one of the existing digital circuits, T flip-flop circuit, is proposed using QCA. The previously proposed T flip-flops are designed based on the majority gate, so the circuits are complex and have long delays. Therefore, the design of the XOR gate-based T flip-flop using cell interaction reduces circuit complexity and minimizes latency. The proposed circuit is simulated using QCADesigner, and the performance is compared and analyzed with the existing proposed circuits.

• Progress in Superconductivity
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• v.4 no.1
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• pp.1-9
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• 2002

Transferring single flux quanta across a Josephson junction at an exactly determined rate has made highly precise voltage measurements possible. Making use of self-shunted Nb-based SINIS junctions, programmable fast-switching DC voltage standards with output voltages of up to 10 V were produced. This development is now extended from fundamental DC measurements to the precise determination of AC voltages with arbitrary waveforms. Integrated RSFQ circuits will help to replace expensive semiconductor devices for frequency control and signal coding. Easy-to-handle AC and inexpensive quantum voltmeters of fundamental accuracy would be of interest to industry. In analogy to the development in the flux regime, metallic nanocircuits comprising small-area tunnel junctions and providing the coherent transport of single electrons might play an important role in quantum current metrology. By precise counting of single charges these circuits allow prototypes of quantum standards for electric current and capacitance to be realised. Replacing single electron devices by single Cooper pair circuits, the charge transfer rates and thus the quantum currents could be significantly increased. Recently, the principles of the gate-controlled transfer of individual Cooper pairs in superconducting A1 devices in different electromagnetic environments were demonstrated. The characteristics of these quantum coherent circuits can be improved by replacing the small aluminum tunnel Junctions by niobium junctions. Due to the higher value of the superconducting energy gap ($\Delta_{Nb}$ ＝ $7\Delta_{Al}$), the characteristic energy and the frequency scales for Nb devices are substantially extended as compared to A1 devices. Although the fabrication of small Nb junctions presents a real challenge, the Nb-based metrological devices will be faster and more accurate in operation. Moreover, the Nb-based Cooper pair electrometer could be coupled to an Nb single Cooper pair qubit which can be beneficial for both, the stability of the qubit and its readout with a large signal-to-noise ratio..

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.11
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• pp.1125-1131
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• 2011

This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.