• Title/Summary/Keyword: Circuit testing

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STATISTICAL ALGORITHMS FOR ENGINE KNOCK DETECTION

  • Stotsky, A.
    • International Journal of Automotive Technology
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    • v.8 no.3
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    • pp.259-268
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    • 2007
  • A knock detection circuit that is based on the signal of an accelerometer installed on the engine block of a spark ignition automotive engine has a band-pass filter with a certain frequency as a parameter to be calibrated. A new statistical method for the determination of the frequency which is the most suitable for the knock detection in real-time applications is proposed. The method uses both the cylinder pressure and block vibration signals and is divided into two steps. In both steps, a new recursive trigonometric interpolation method that calculates the frequency contents of the signals is applied. The new trigonometric interpolation method developed in this paper improves the performance of the Discrete Fourier Transformation, allowing a flexible choice of the size of the moving window. In the first step, the frequency contents of the cylinder pressure signal are calculated. The knock is detected in the cylinder of the engine cycle for which at least one value of the maximal amplitudes calculated via the trigonometric interpolation method exceeds a threshold value indicating a considerable amount of oscillations in the pressure signal; this cycle is selected as a knocking cycle. In the second step, the frequency analysis is performed on the block vibration signal for the cycles selected in the previous step. The knock detectability, which is an individual cylinder attribute at a certain frequency, is verified via a statistical hypothesis test for testing the equality of two mean values, i.e. mean values of the amplitudes for knocking and non-knocking cycles. Signal-to-noise ratio is associated in this paper with the value of t-statistic. The frequency with the largest signal-to-noise ratio (the value of t-statistic) is chosen for implementation in the engine knock detection circuit.

A Novel Third-Order Cascaded Sigma-Delta Modulator using Switched-Capacitor (스위치형 커패시터를 이용한 새로운 형태의 3차 직렬 접속형 시그마-델타 변조기)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.1
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    • pp.197-204
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    • 2010
  • This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

New ADD Injection Driven Transonic Wind Tunnel and Test With the AGARD Model (신규 건설 ADD 천음속풍동 소개 및 AGARD 표준모형 공력계수 비교)

  • Seo, Kyugnwon;Lee, Jong Geon;Shin, Seongbeom;Han, Sang Hyun;Park, Keum Yong;Kim, Young Jun;Kim, Namgyun;Jin, Hyeon
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.48 no.2
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    • pp.119-125
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    • 2020
  • A high Reynolds number transonic wind tunnel has been built in 2018 at Agency for Defense Development(ADD). The tunnel has a closed circuit with a 1.5m×1.5m test section and is injection driven from a 140bar air supply system. The Mach number range is 0.3-1.2 with a conventional contracting nozzle and 1.4 with a convergent-divergent contraction. The stagnation pressure range is 100-550kPa at the lowest Mach number. An AGARD-B standard model is tested in the transonic wind tunnel to obtain 6-DOF aerodynamic coefficients. The results are compared with those obtained from ADD trisonic wind tunnel and others. We verify that the transonic wind tunnel become available to develop an aircraft from the testing results.

Failure Mechanism Analysis of SAW Device under RF High Power Stress (RF 고전력 스트레스에 의한 SAW Device의 고장메카니즘 분석)

  • Kim, Young-Goo;Kim, Tae-Hong
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.5
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    • pp.215-221
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    • 2014
  • In this paper, the improved power durability test system and method for an reliability analysis of SAW device is proposed and the failure mechanism through failure analysis is analyzed. As a result of the failure analysis using microscope, SEM and EDX, the failure mechanism of the SAW device is electromigration due to joule heating under high current density and high temperature condition. The electromigration makes voids and hillocks in the IDT electrode and the voids and hillocks can lead to short circuit and open circuit faults, respectively, increasing the insertion loss of an SAW filter. The accelerated life testing of the SAW filter for 450MHz CDMA application using the proposed power durability test system and method is carried out. $B_{10}$ lifetime of the SAW filter using Eyring model and Weibull distribution is estimated as about 98,500 hours.

A New Design of Power Folding Controller for Deterioration Detection (열화방지형 파워폴딩 제어기 설계에 관한 연구)

  • Kim, Ji-Hyeon;Lee, Dong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.45 no.3
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    • pp.51-58
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    • 2008
  • This paper is a study of a prevention of power folding controller's thermal degradation. Power folding technology has been applied for many fields such as side rear vision mirror of vehicles, windshield wiper, antenna, power window. These controllers have been comprised with traditional DC moors, Switching electronic devices, and relays. But this methods have a limitation to overcome such problems of product reliability, endurance, noise margins. Therefore on this paper, to detect the movement of motor, sensing motor brush noise on a load sensing part has been used and controlling a precise RC timing control minimizes the thermal deterioration of motor. And using MOS FETs as a electronic switching device increases life-time and liability of control circuit. After testing such circuit and control method, repetition of operating time, cut-off time, wide operation voltage, power noise margin ware increased over eleven-fold.

A Design of All-Digital QPSK Demodulator for High-Speed Wireless Transmission Systems (고속 무선 전송시스템을 위한 All-Digital QPSK 복조기의 설계)

  • 고성찬;정지원
    • Journal of Korea Society of Industrial Information Systems
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    • v.8 no.1
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    • pp.83-91
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    • 2003
  • High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

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An FPGA Design of High-Speed QPSK Demodulator (고속 무선 전송을 위한 QPSK 복조기 FPGA 설계)

  • 정지원
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.12
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    • pp.1248-1255
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    • 2003
  • High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6[Mbps]. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

Design of Stack Monitoring System with Improved Performance (성능이 향상된 Stack Monitoring System의 설계)

  • Jang, Kyeong-Uk;Lee, Joo-Hyun;Lee, Seong-Won;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.20 no.3
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    • pp.299-302
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    • 2016
  • In this paper, we designed the stack monitoring system with improved performance. To block the incoming pulse noise to the amplifier, shield and the power supply impedance are reduced and the power circuit is isolated. The control unit is developed with variable high voltage, adaptive gain, offset and threshold in order to match the scintillation detector characteristic to the apparatus. 300-1500V variable high voltage power circuit is configured applicable to various scintillation detector. Stack monitoring system with improved performance guarantee the efficiency and the reliability by considering the characteristic of various scintillation detector. Developed stack monitoring system is evaluated with certified testing equipment and shows excellent performance with respect to the uncertainty of the sensor test results.

New On-Chip RF BIST(Built-In Self Test) Scheme and Circuit Design for Defect Detection of RF Front End (RF Front End의 결함 검출을 위한 새로운 온 칩 RF BIST 구조 및 회로 설계)

  • 류지열;노석호
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.2
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    • pp.449-455
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    • 2004
  • This paper presents a novel defect detection method for one chip RF front end with fault detection circuits using input matching measurement. We present a BIST circuit using 40.25{\mu}m$ CMOS technology. We monitor the input transient voltage of the RF front end to differentiate faulty and fault-free RF front end. Catastrophic as well as parametric variation fault models are used to simulate the faulty response of the RF front end. This technique has several advantages with respect to the standard approach based on current test stimulus and frequency domain measurement. Because DUT and fault detection circuits are implemented in the same chip, this test technique only requires use of digital voltmeter (RMS meter) and RF voltage source generator for simpleand inexpensive testing.

A Study on the Development of Low Pass Filter for Chopper Gate Control Unit of Electric Rolling Stock (부산도시철도 1호선 전동차 Low Pass Filter 개발연구)

  • Kang, Hyun-Chul;Kim, Hae-Chang;Park, Hee-Chul
    • Proceedings of the KSR Conference
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    • 2011.05a
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    • pp.1445-1456
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    • 2011
  • This paper presents the research of Low Pass Filter(hereinafter called "LPF") which is the part of Chopper Gate Control Unit on the electric rolling stock. Chopper Gate Control Unit controling the propulsive equipments of electric rolling stock consists of several electronic parts, PCB, Power Supply, Gate Circuit Amp, Freon Cooling Device, and has been used the parts made by japan manufacturer Mitsubish. But these parts recently have been more broken down and slow down performance because of long-term use, deterioration. Most of the malfunctions are low performance of LPF. Furthermore, it is physically impossible to repair LPF. Because it is molding type part and no longer manufactured. Also it needs high cost for custom-building. Therefore, it is now making up for through self-developed LPF and operating on Busan metro 1st after on-board testing. This research performed the PS Pice simulation testing, analysis of self-developed LPF performance and the wave form characteristic by multi-function synthesizer, spectrum analyzer, oscilloscope.

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