• Title/Summary/Keyword: Circuit testing

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Introduction of the field - test evaluation system in KEPCO (배전 실증시험장 시스템 현황 소개)

  • Kim, Dong-Myung;Choi, Sun-Kyu;Jang, Sang-Ok;Oh, Jae-Hyoung
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2004.05a
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    • pp.81-85
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    • 2004
  • This paper describes the testing facility to demonstrate the performance of the distribution class circuit breakers and switchgears and the testing methods. The field-test evaluation system consists of two parts. One is the distribution system for simulation of the condition on interruption mode of switches which are installed in the system and tested by the AFG(Artificial Fault Generator) and the thunderbolt generator just like in the real field. The other is a laboratory for confirmation or the important characteristics regarding to the insulation, gas, environment durability of equipment. For the fatal failure mode, a FMEA(Failure Modes and Effects Analysis) technique which is a kind of a structural analysis to consider a counter-plan was emploved.

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Low Power Test for SoC(System-On-Chip)

  • Jung, Jun-Mo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.10a
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    • pp.892-895
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    • 2011
  • Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

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Study for analyzing decisive factors on short circuits of testing laboratory with short circuit generator using super excitation(I) (발전기 과여자를 고려한 단락시험회로의 회로특성 결정인자 분석연구(I))

  • Ahn, Sang-Ho
    • Proceedings of the KIEE Conference
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    • 2003.11a
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    • pp.7-9
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    • 2003
  • 전력계통의 정상상태와 다양한 초장상태를 모의하기위한 단락시험설비는 크게 단락발전기, 보호차단기, 전류제한 리액터, 투입스위치, 단락변압기, 버스바 및 케이블, 투입피크 제한장치, 부하회로 및 측정장치 등으로 구성되어 있으며, 유효한 시험을 위해서는 이러한(변수)조합들을 적절하게 조절, 제어하여 실계통의 현상을 재현하거나 규격 또는 의뢰자의 요구에 부응하도록 하는 것이 중요하다. 이것을 위해서는 각 시험설비의 정상 및 과도 특성과 조합된 회로에 상존하는 변수(stray values)들을 찾아내고, 이들에 대한 독립성과 의존성 관계를 파악하여 계산 가능한 모델링을 도출 하여야 한다. 그러나 경험적으로 볼때 단락발전기의 과도임피던스 및 여자 특성과 변압기를 포함한 회로상의 stray values 등이 여러 변수들과 만들어내는 상관관계를 파악하는데는 좀 어려움이 있었다. 본 논문에서는 이러한 관점에서 상기 변수에 따른 변화 기여도를 가능한 한 정량적으로 분석하여 회복전압, TRV 및 전류와의 상관관계를 규명해 보고자 한다.

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Built-In Self-Test of DAC using CMOS Structure (CMOS 구조를 이용한 DAC의 자체 테스트 기법에 관한 연구)

  • Cho, Sung-Chan;Kim, In-Soo;Min, Hyoung-Bok
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.1862-1863
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    • 2007
  • Testing the analog/mixed-signal circuitry of a mixed-signal IC has become a difficult task. Offset error, gain error, Non-monotonic behavior, Differential Non-linearity(DNL) error, Integral Non-linearity(INL) error are important specifications used as test parameters for DAC. In this paper, we propose an efficient BIST structure for DAC testing. The proposed BIST adds the circuit which uses the capacitor and op-amp, and accomplishes a test.

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Mechanical Life Prediction of a Relay by Accelerated Life Tests (가속시험에 의한 릴레이의 기계적 수명평가에 관한 연구)

  • Kwon Young-Il;Han In-Su
    • Proceedings of the Korean Reliability Society Conference
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    • 2005.06a
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    • pp.75-82
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    • 2005
  • In this paper, accelerated life testing(ALT) method and procedures for a are developed and applied to assess the reliability of the product. Relay is a device that can open and close the electric circuit electrically and is used for protecting and controlling the load. In this study, an accelerated life test method for predicting the mechanical life of a relay is developed using the relationship between stresses, failure mechanism and life characteristics of products. Using the ALT method, we performed life tests and analyzed the tests results. The proposed method and procedures may de extended and applied to testing similar kinds of products to reduce test times and costs of the tests remarkably.

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Geometric calibration of a computed laminography system for high-magnification nondestructive test imaging

  • Chae, Seung-Hoon;Son, Kihong;Lee, Sooyeul
    • ETRI Journal
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    • v.44 no.5
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    • pp.816-825
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    • 2022
  • Nondestructive testing, which can monitor a product's interior without disassembly, is becoming increasingly essential for industrial inspection. Computed laminography (CL) is widely used in this application, as it can reconstruct a product, such as a printed circuit board, into a three-dimensional (3D) high-magnification image using X-rays. However, such high-magnification scanning environments can be affected by minute vibrations of the CL device, which can generate motion artifacts in the 3D reconstructed image. Since such vibrations are irregular, geometric corrections must be performed at every scan. In this paper, we propose a geometry calibration method that can correct the geometric information of CL scans based on the image without using geometry calibration phantoms. The proposed method compares the projection and digitally reconstructed radiography images to measure the geometric error. To validate the proposed method, we used both numerical phantom images at various magnifications and images obtained from real industrial CL equipment. The experiment results confirmed that sharpness and contrast-to-noise ratio (CNR) were improved.

An Efficient Built-in Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories

  • Kang, Dong-Chual;Park, Sung-Min;Cho, Sang-Bock
    • ETRI Journal
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    • v.26 no.6
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    • pp.520-534
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    • 2004
  • As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

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Novel Claw Pole Eddy Current Load for Testing DC Counter Rotating Motor - Part II: Design and Modeling

  • Kanzi, Khalil;Roozbehani, Sam;Dehafarin, Abolfazl;Kanzi, Majid
    • Journal of international Conference on Electrical Machines and Systems
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    • v.1 no.4
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    • pp.412-418
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    • 2012
  • Eddy current brakes are electromechanical devices used as variable mechanical loads for testing electrical machines. Accurate modeling of eddy current loss is an important t factor for optimum design of eddy brake systems. In this second part, we propose novel formulations of eddy current loss in novel claw-pole eddy brake system. The proposed model for eddy current loss in novel claw-pole eddy brake system depends on the size of the claw poles. Also, in this paper, the flux density is measured by using the magnetic circuit of the novel claw pole. The model results are compared with experimental results and they are found to be in good agreement.

Automatic BIST Circuit Generator for Embedded Memories (내장 메모리 테스트를 위한 BIST 회로 자동생성기)

  • Yang, Sunwoong;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.10
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    • pp.746-753
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    • 2001
  • GenBIST implemented in this paper is an automatic CAD tool, which can automatically generate circuitry in VerilogHDL code based on user defined information for the memory testing. While most commercial and conventional CAD tools adopt a method in which they make memory-testing algorithms as a library to generate circuitry, our tool can generate circuitry according to the user-defined algorithm, which makes application of various algorithms easier. In addition, memory BIST circuitry can be shared with other memories by supporting embedded memories in our tool. Also, extra pins for the memory testing are not requited when boundary scan technique is combined.

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Analysis of multiple spurious operation scenarios of Korean PHWRs using guidelines of nuclear power plants in U.S.

  • Kim, Jaehwan;Jin, Sukyeong;Kim, Seongchan;Bae, Yeonkyoung
    • Nuclear Engineering and Technology
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    • v.51 no.7
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    • pp.1765-1775
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    • 2019
  • Multiple spurious operations (MSOs) mean multiple fire induced circuit faults causing an undesired operation of one or more systems or components. The Nuclear Energy Institute (NEI) of the United States published NEI 00-01 as guidelines for solving MSOs. And this guideline includes MSO scenarios of pressurized water reactor (PWR) and boiling water reactor (BWR). Nuclear power plant operators in U.S. analyzed MSOs under MSO scenarios included in NEI 00-01 and operators of PWRs in Korea also analyzed MSOs under the scenarios of NEI 00-01. As there are no pressurized heavy water reactors (PHWRs) in the United States, MSO scenarios of PHWRs are not included in the NEI 00-01 and any feasible scenarios have not been developed. This paper developed MSO scenarios which can be applied to PHWRs by reviewing the 63 MSO scenarios included in NEI 00-01. This study found that seven scenarios out of the 63 MSO scenarios can be applied and three more scenarios need to be developed.