• Title/Summary/Keyword: Circuit testing

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BIST implemetation with test points insertion (테스트 포인트 삽입에 의한 내장형 자체 테스트 구현)

  • 장윤석;이정한김동욱
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1069-1072
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    • 1998
  • Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

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A study on monitor filter PLC monitor device PON system (PON 시스템 감시 모니터용 PLC 소자)

  • Choi, Young-Bok;Park, Soo-Jin;Koh, Seok-Bong;Lee, Bong-Young
    • 한국정보통신설비학회:학술대회논문집
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    • 2007.08a
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    • pp.22-26
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    • 2007
  • In the fibre to the home (FTTH) era, it is expected that broadband network provisioning will require thousands of optical fibres to be accommodated in a central office for optical access networks. An optical fibre line testing system could be used to reduce maintenance costs and improve service availability depending on the PON's element manager capabilities and the maintenance procedures adopted by the network supplier. When monitoring optical fibres transmitting communication lights, a wavelength of 1625 nm is used for maintenance testing. The splitter installed optical filters allow the communication light to pass but that cut off the test light in the front of optical line terminals (OLTs) and optical network terminals (ONTs). In the economic point of view, We design new planer lightwave circuit splitter embedded filtter and study it optical property.

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A Study of Minimum Ignition Energy Measurement of Explosive Powders Caused by Electrostatic Discharges (정전기 방전시의 분체류의 최소착화에너지 측정에 관한 연구)

  • 이동훈;목연수;최재욱;신중현;류상민;조일건;정준채
    • Proceedings of the Korean Institute of Industrial Safety Conference
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    • 1997.05a
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    • pp.67-75
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    • 1997
  • To establish testing method for ignition energy of explosive powders caused by electrostatic discharge, one testing method using a very small quantity of tested powders ( Frima ) was proposed, and the influence of discharge - limiting resistance connected in series into a capacitive discharge circuit on ignition energies of explosive powders was investigated using, as tested powders. As a result the minimum ignition energy was 9 mJ when discharge-limiting resistance was 300 k$\Omega$. The reason for the dependence of ignition energy on discharge-limiting resistance was thought to the difference in the type of electrostatic discharge, such as arc or glow discharge, from the observation of discharging wave forms.

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A Study for the results of electric characteristic and performance tests of LGIS short-circuit generator (LG산전 단락발전기의 전기적 특성 및 성능시험과 고찰)

  • Lee, Hee-Cheol;Han, Gyu-Hwan
    • Proceedings of the KIEE Conference
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    • 2000.07a
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    • pp.567-569
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    • 2000
  • 대전력시험 설비 중 단락발전기는 시험에 필요한 에너지를 발생시키는 근원으로서 시험하고자 하는 피시품의 시험용량에 따라 설계되고 제작되어야 한다. 본 논문에서는 LG산전 대전력시험 설비 중 단락발전기에 대한 설계 개념, 전기적 및 기계적인 특성, 또한 일반 발전기와는 다르게 특별히 설계된 주요 특징 등에 대하여 기술하며, 피시품의 단락시험 중에 발생하는 시험 시퀀스 및 이에 대한 기술적인 내용을 기술한다. 또한, 단락발전기의 시운전 및 성능 확인 시험 결과에 대한 내용을 기술하고, 시험 중 발생할 수 있는 내용에 대하여 고찰하여 본다.

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Test Time Reduction of BIST Using Internal Nodes of a Circuit (회로 내부 노드를 이용한 BIST의 테스트 시간 감소)

  • 최병구;장윤석;김동욱
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.397-400
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    • 1999
  • As the result of enhancement of CAD, Design Automation and manufacturing technology, it's on the increasing complexity, integration ratio, data signals, and pin count to IC chips. This brings about difficulties of testing, and incresing test time. Now One of the most cost-consuming procedure as integration ratio increases is the testing step. In this paper, we propose a new method, “Efficient TP(test point) assignment algorithm” using “input grouping”, This is helpful method to reducing test length without losing fault coverage. Experimental results show that proposed method reduces test length remarkably and doesn't miss fault coverage, with low hardware overhead Increasing.

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BIST Design for Hazard controller in Pipeline System (Pipeline 시스템의 Hazard 검출기를 위한 BIST 설계)

  • 이한권;이현룡;장종권
    • Proceedings of the IEEK Conference
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    • 2003.11b
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    • pp.27-30
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    • 2003
  • The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

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Fabrication and Testing of a Polysilicon Piezoresistive Accelerometer using p+ Silicon Diaphragm (p+ 실리콘 박막을 이용한 폴리실리콘 압저항 가속도계의 제작 및 측정)

  • Yang, E.H.;Jeong, O.C.;Yang, S.S.
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1994-1996
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    • 1996
  • This paper presents the fabrication and testing of a polysilicon piezoresistive accelerometer with p+ silicon diaphragm by simple process such as two step photolithography for the RIE process to form the cantilevers and a deep anisotropic etch process for the complete fabrication of the accelerometer. The fabricated accelerometer consists of a seismic mass and four cantilevers on which polysilicon piezoresistors are formed. The measurement of the output signal from the bridge circuit of the fabricated accelerometer is carried out with the HP 3582A spectrum analyzer. The analysis of the experimental result is showed in terms of the sensitivity and the resonant frequency. At atmospheric condition, the measurement values of the sensitivity and the resonant frequency are $11\;{\mu}V/Vg$ and 475 Hz, respectively.

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Fatigue Test of MEMS Device: a Monolithic Inkjet Print

  • Park, Jun-Hyub;Oh, Yong-Soo
    • Journal of Mechanical Science and Technology
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    • v.18 no.5
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    • pp.798-807
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    • 2004
  • A testing system was developed to improve the reliability of printhead and several printheads were tested. We developed a thermally driven monolithic inkjet printhead comprising dome-shaped ink chambers, thin film nozzle guides, and omega-shaped heaters integrated on the top surface of each chamber. To perform a fatigue test of an inkjet printhead, the testing system automatically detects a heating failure using a Wheatstone bridge circuit. Various models were designed and tested to develop a more reliable printhead. Two design parameters of the width of reinforcing layer and heater were investigated in the test. Specially., the reinforcing layer was introduced to improve the fatigue life of printhead. The life-span of heater with a reinforcing layer was longer than that without a reinforcing layer. The wider the heater was, the longer the life of printhead was.

Design of performance testing device for heat exhaust ventilation fan (제연용 송풍기의 방염성능 시험장치 설계)

  • Lee, Young-Mo;Kim, Kwang-Yong;Lee, Jae-Yup;Jung, Hyun-Jong
    • 유체기계공업학회:학술대회논문집
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    • 2005.12a
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    • pp.367-372
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    • 2005
  • This study primarily is concerned with a new device which has been developed following the international standards to measure the ventilation performance at elevated temperature. This device can measure duration of ventilation, performance of electricity, static pressure at elevated temperature and also it is having provision to measure reversible performances during fire hazards. Invented device is closed circuit type system which is best suited for korean industrial environment with low cost and high efficiency. International standards has been compared and performance testing has been major using BS 7346 which is tested by Warrington Fire Research Centre.

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Development of an active gust generation mechanism on a wind tunnel for wind engineering and industrial aerodynamics applications

  • Haan, Fred L. Jr.;Sarkar, Partha P.;Spencer-Berger, Nicholas J.
    • Wind and Structures
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    • v.9 no.5
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    • pp.369-386
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    • 2006
  • A combination Aerodynamic/Atmospheric Boundary Layer (AABL) Wind and Gust Tunnel with a unique active gust generation capability has been developed for wind engineering and industrial aerodynamics applications. This facility is a cornerstone component of the Wind Simulation and Testing (WiST) Laboratory of the Department of Aerospace Engineering at Iowa State University (ISU). The AABL Wind and Gust tunnel is primarily a closed-circuit tunnel that can be also operated in open-return mode. It is designed to accommodate two test sections ($2.44m{\times}1.83m$ and $2.44m{\times}2.21m$) with a maximum wind speed capability of 53 m/s. The gust generator is capable of producing non-stationary gust magnitudes around 27% of the mean flow speed. This paper describes the motivation for developing this gust generator and the work related to its design and testing.