• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.4
• /
• pp.273-279
• /
• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1036-1039
• /
• 2009

We have developed an automated circuit defect repair method. We focused on the resist patterns on the circuit material layer of TFT substrates before the etching process. In this paper, we report on the repair method that utilizes the syringe system and the stability of the open defect repair process.

• Journal of Information Display
• /
• v.10 no.4
• /
• pp.202-205
• /
• 2009

An automated circuit repair system was developed for enhancing the yield of nondefective liquid crystal panels, focusing on the resist patterns on the circuit material layer of thin-film transistor (TFT) substrates prior to etching. The developed system has an advantage over the parallel conventional system: In the former, the repair conditions depend on the type of resist whereas in the latter, the repair parameters must be fine-tuned for each circuit material. The developed system consists of a resist pattern defect inspection system and a pattern repair system for short and open defects. The repair system performs fine corrections of abnormal areas of the resist pattern. The open-repair system is equipped with a syringe to dispense resist. To maintain a stable resist diameter, a thermal insulator was installed in the syringe system. As a result, the diameter of the dispensed resist became much more stable than when no thermal insulator was used. The resist diameter was kept within the target of $400{\pm}100{\mu}m$. Furthermore, a prototype system was constructed, and using a dummy pattern, it was confirmed that the system worked automatically and correctly.

• Journal of Practical Engineering Education
• /
• v.8 no.2
• /
• pp.91-94
• /
• 2016

This study is focused on the development and application of automotive lighting system simulator device to help understanding of the repair and overhaul, electrical instrumentation and automotive circuit checks the contents of the automotive electrical system. The purpose of this study is to define the circuit numeracy, circuit repair preparation skills, detachable power, circuit analysis capabilities, inspection and measurement capability, and repair (problem solving) skills, through the cultivation of clean ability to increase the understanding of electrical equipment maintenance circuitry to verify the improvement of the repair. Automotive electrical device requires understanding of the invisible parts, and understanding of the various symbols and complex circuitry to measure the basic checks and repair are indispensable. This paper would likely contribute to help students to gain more interest in the fields that they feel difficult such as basic skills which necessary to cultivate a variety of electrical equipment fault diagnosis of the basic knowledge needed for electric cars practical.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.8
• /
• pp.1877-1886
• /
• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of information and communication convergence engineering
• /
• v.9 no.5
• /
• pp.615-618
• /
• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.54-60
• /
• 2007

This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.322-330
• /
• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.48-55
• /
• 2010

As the complexity and the clock speed of semiconductor integrated circuits increase, silicon validation becomes important. In this research, we developed new post-silicon repair & revision techniques to reduce cost and time-to-market. Spare cells are fabricated with the original design and are used for repair when necessary. The interconnections are modified by repair layer revision. The repair cost can be reduced by logic partitioning. Experimental results show that these techniques are effective for low-cost and fast turnaround repair.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.286-289
• /
• 2007

We have developed an automated circuit defect inspection and repair method that can be used to improve the yield ratio of TFT-LCD. The method focuses on correcting resist patterns after the development process to ensure shape regularity. We built a prototype system and confirmed that the method is valid.