• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권2호
• /
• pp.162-167
• /
• 2012

This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2017년도 추계학술대회
• /
• pp.43-44
• /
• 2017

This paper presents design of auxiliary circuit to reduce loss of ZVT interleaved flyback converter. The ZVT interleaved converter using the conventional auxiliary circuit has a large conduction loss due to the constant circulating current in the auxiliary circuit. The auxiliary circuit proposed in this paper, which consists of the coupled inductor and DC-link capacitor, has linearly increasing or decreasing auxiliary current. Then, the conduction loss occurring in the auxiliary circuit is reduced. The validity of the proposed auxiliary circuit is verified with the prototype of 500W.

• 한국군사과학기술학회지
• /
• 제12권3호
• /
• pp.282-289
• /
• 2009

This paper presents an estimation technique of the equivalent circuit parameters for an underwater acoustic piezoelectric transducer from the measured impedance. Estimated equivalent circuit can be used for the design of the impedance matching network of the sonar transmitter. A fitness function is proposed to minimize the error between the calculated impedance of the equivalent circuit and the measured impedance of the transducer. The equivalent circuit parameters are estimated by using the fitness function and the PSO(Particle Swarm Optimization) algorithm. The effectiveness of the proposed method is verified by the applications to a sandwich-type transducer and a dummy load. In addition, the impedance matching network is also designed by using the estimated equivalent circuit model.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.947-950
• /
• 1999

The PLD design of new scheme LCD driver circuit is described in this paper. A new scheme LCD driver circuit doesn't used microprocessor for the convenience of users. A new scheme LCD driver circuit consists of 4 main parts, that is, a serial/parallel communication control block part, a LCD controller part, a LCD driver part and a RAM/ROM control block part. The validity and efficiency of the proposed LCD driver circuit have been verified by simulation and by ALTERA EPM7192SQC160-15 PLD implementation in VHDL. After comparing this LCD driver circuit to specify it was verified that the developed LCD driver circuit showed has good performances, such as low cost, convenience of users.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
• /
• pp.410-413
• /
• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was DuPont #9599, which is applied for L TCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of l0[mA]

• 한국초전도저온공학회:학술대회논문집
• /
• 한국초전도저온공학회 2003년도 추계학술대회 논문집
• /
• pp.123-126
• /
• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집
• /
• pp.410-413
• /
• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was Dupont ＃9599, which is applied for LTCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of 10[mA].

• Transactions on Electrical and Electronic Materials
• /
• 제1권3호
• /
• pp.1-5
• /
• 2000

This paper presents a new sort of multilayer piezoelectric ceramic transformer for switching regulation power supplies. This piezoelectric transformer operate in the second thickness resonant vibration mode. Accordingly its resonant frequency is higher than 1 NHz, Because output power is low if input and output part of transformer are consisted of single layer, this research suggests a new method, which is consisted of both input and output part of transformer have 2-layered piezoelectric ceramics, The size of transformer is 20 mm in width and length, and 1.4 mm in thickness, respectively, To design a high efficient switching circuit of the transformer, internal circuit parameters were measured and then weve calculated a parameter of inductor nd capacitor to design a driving circuit, Weve used a MISFET and its driver circuit modified a calp oscillator circuit as the primary switching circuit.

• 전자공학회논문지B
• /
• 제30B권11호
• /
• pp.1-10
• /
• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -1
• /
• pp.470-473
• /
• 2002

A communication-aid circuit to detect eye-gazed patterns is proposed in this paper. The circuit is an analog-digital mixed system. By determining the direction of eye-gazed pattern, the circuit detects an eye-gazed pattern from 2-dimensional arrayed patterns on a syllabary. Different from conventional systems, the syllabary is moved to overlap the eye-gazed pattern with the center coordinate of screen. Thus, the proposed circuit can avoid a complex calculation of the distance between the eye-gazed point and the center coordinate. Furthermore: an economical size of hardware can be provided since no full-adders are required by employing floating-gate MOSFBT's. The validity of the cricuit design is confirmed by computer simulations. Furthermore, to implement onto an IC chip, the layout design is performed by using a CAD tool, MAGIC.