• 전기학회논문지
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• 제62권6호
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• pp.798-802
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• 2013

In a conventional DC power supply used for CO2 laser, the circuit elements such as a rectifier bridge, a current-limiting resistor, a high voltage switch, energy storage capacitors ans a high-voltage isolation transformer using high turn ratio are necessary. Consequently, those supplies are expensive and require a large space. Thus, laser resonator and power supply should be optimally designed. In this paper, we propose a new power supply using high frequency resonance phenomena for CW(Continuous wave) CO2 laser (maximum output of 23W with discharge length of 450mm). It consists of a transformer including leakage inductance, magnetizing inductance and half-bridge converter, a three-stage Cockcroft-Walton and PFC(Power factor correction) circuit. The output ripple voltage can be controlled the minimum of 0.24% under the high frequency switching of 231kHz. Furthermore, the output efficiency was improved to 16.4% and the laser output stability of about 5.6% was obtained in this laser system.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.891-895
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• 2004

This paper suggests the techniques in determining the values of the steady-state equivalent circuit parameters of a three-phase squirrel-cage induction machine using immune algorithm. The parameter estimation procedure is based on the steady state phase current versus slip and input power versus slip characteristics. The proposed estimation algorithm is of a nonlinear kind based on clonal selection in immune algorithm. The machine parameters are obtained as the solution of a minimization of least-squares cost function by immune algorithm. Simulation shows better results than the conventional approaches.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.537-539
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• 1996

In this paper, a design method of the phase shift ZVS-PWM converter is proposed to minimize the volume and increase the efficiency. The trade-offs of switching frequency, efficiency vs volume and ZVS range vs efficiency is also presented. The simulation of the designed converter is performed using the P-SPICE in which a phase-shift controller is proposed. For minimization of the converter volume, switching frequency is selected 100kHz, a simple drive circuit and single auxiliary supply are applied. In consideration of efficiency and load condition, ZVS range is decided from 50% to full load. A 28V, 1Kwatt prototype converter, of which the switch is MOSFET is made, verified the performance.

• 한국컴퓨터정보학회논문지
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• 제21권3호
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• pp.57-64
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• 2016

This paper deals with the PCB assembly time minimization problem that the PAP (pick-and-placement) machine pickup the K-weighted group of N-components, loading, and place into the PCB placement location. This problem considers the rotational turret velocity according to component weight group and moving velocity of distance in two component placement locations in PCB. This paper suggest heavy-weight component group first pick-and-place strategy that the feeder sequence fit to the placement location Hamiltonean cycle sequence. This algorithm applies the quadratic assignment problem (QAP) that considers feeder sequence and location sequence, and the linear assignment problem (LAP) that considers only feeder sequence. The proposed algorithm shorten the assembly time than iATMA for QAP, and same result as iATMA that shorten the assembly time than ATMA.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2004년도 추계학술대회 학술발표 논문집 제14권 제2호
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• pp.21-25
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• 2004

This paper suggests the techniques in determining the values of the steady-state equivalent circuit parameters of a three-phase squirrel-cage induction machine using immune algorithm. The parameter estimation procedure is based on the steady state phase current versus slip and input power versus slip characteristics. The proposed estimation algorithm is of a nonlinear kind based on clonal selection in immune algorithm. The machine parameters are obtained as the solution of a minimization of least-squares cost function by immune algorithm. Simulation shows better results than the conventional approaches.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.669-672
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• 2003

With the advances on wireless internet technology, many research on minimization of wireless LAN is on the progress. To apply passive components in MCM, characteristic analysis of passive components is essential. In this paper, three square spiral inductors were modeled by HSPICE using PEEC (Partial Element Equivalent Circuit) method. Afterwards, Monte-Carlo analysis was performed to evaluate the optimized parameters. This work will give an idea on PEEC modeling of spiral inductor, and enable researchers with predictive data before large scale manufacturing.

• 전자공학회논문지A
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• 제33A권11호
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• pp.128-139
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• 1996

In this paper, we propose an algorithm to solve the problem of placement of rectangular blocks whose sizes and shpaes are pre-determined. The proposed method solves the placement of many retangular blocks of different sizes and shapes in a hierarchical manner, so as to minimize the chip area. The placement problem is divided into several sub-problems: hierarchical partioning, hierarchical area/shape estimation, hierarchical pattern pacement, overlap removal, and module rotation. After the circuit is recursively partitioned to build a hierarchy tree, the necessary wiring area and module shpaes are estimated using the resutls of the partitioning and the pin information before the placement is performed. The placement templaes are defined to represent the relative positions of the modules. The area and the connectivity are optimized separately at each level of hierachy using the placement templates, so the minimization of chip area and wire length can be achieved in a short execution time. Experiments are made on the MCNC building block benchmark circuits and the results are compared with those of other published methods. The proposed technique is shown to produce good figures in tems of execution time and chip area.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• 한국공작기계학회논문집
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• 제17권3호
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

• Journal of Welding and Joining
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• 제15권6호
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• pp.105-115
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• 1997

A numerical study is performed to predict the thermal response of a detailed card assembly during infrared reflow soldering. The card assembly is exposed to discontinuous infrared panel heater temperature distributions and high radiative/convective heating and cooling rates at the inlet and exit of the oven. The convective, radiative and conduction heat transfer within the reflow oven as well as within the card assembly are simulated and the predictions illustrate the detailed thermal responses. The predictions show that mixed convection plays an important role with relatively high frequency effects attributed to buoyancy forces, however the thermal response of the card assembly is dominated by radiation. The predictions of the detailed card assembly thermal response can be used to select the oven operating conditions to ensure proper solder melting and minimization of thermally induced card assembly tresses and warpage.