• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.2
• /
• pp.365-370
• /
• 2004

In this paper, complexity secure communication was presented. The complexity circuit is used to State-Controlled Cellular Neural Network(SC-CNN). We make a complexity circuit using SC-CNN with the N-double scroll. A complexity circuit is created by applying identical n-double scrolls with coupled method, to each cell. complexity synchronization was achieved using drive response synchronization between the transmitter and receiver about each state in the SC-CNN. From the result of the recovery signal through the demodulation method in the receiver. We shown that recovery quality in the receiver is the similar to other secure communication methods.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.3
• /
• pp.137-144
• /
• 2016

In this paper, we have proposed a circuit complexity optimization ILP algorithm of high-level synthesis system for new multiprocessor design. We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the ILP algorithm. We have achieved is that standard benchmark model for the scheduling of the 5th digital wave filter, it was exactly the same due to the existing datapath scheduling results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.3
• /
• pp.319-325
• /
• 2015

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in $0.18{\mu}m$ CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.1
• /
• pp.8-15
• /
• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.3
• /
• pp.145-151
• /
• 2003

This study focuses on the hardware implementation of fast and low-complexity multiplier over GF(2$^{m}$ ). Finite field multiplication can be realized in two steps: polynomial multiplication and modular reduction using the irreducible polynomial and we will treat both operation, separately. Polynomial multiplicative operation in this Paper is based on the Permestzi's algorithm, and irreducible polynomial is defined AOP. The realization of the proposed GF(2$^{m}$ ) multipleker-based multiplier scheme is compared to existing multiplier designs in terms of circuit complexity and operation delay time. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.437-444
• /
• 2015

In simulation-based circuit optimization, many simulation runs may be wasted while evaluating infeasible designs, i.e. the designs that do not meet the constraints. To avoid such a waste, this paper investigates the use of support vector machine (SVM) classifiers in predicting the design's feasibility prior to simulation and the optimal selection of the SVM parameters, namely, the Gaussian kernel shape parameter ${\gamma}$ and the misclassification penalty parameter C. These parameters affect the complexity as well as the accuracy of the model that SVM represents. For instance, the higher ${\gamma}$ is good for detailed modeling and the higher C is good for rejecting noise in the training set. However, our empirical study shows that a low ${\gamma}$ value is preferable due to the high spatial correlation among the circuit design candidates while C has negligible impacts due to the smooth and clean constraint boundaries of most circuit designs. The experimental results with an LC-tank oscillator example show that an optimal selection of these parameters can improve the prediction accuracy from 80 to 98% and model complexity by $10{\times}$.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.4
• /
• pp.1604-1613
• /
• 2018

The paper presents the equivalent circuit of an induction machine (IM) model which includes fundamental stray load and iron losses. The corresponding equivalent resistances are introduced and modeled as variable with respect to the stator frequency and flux. Their computation does not require any tests apart from those imposed by international standards, nor does it involve IM constructional details. In addition, by the convenient positioning of these resistances within the proposed equivalent circuit, the order of the conventional IM model is preserved, thus restraining the inevitable increase of the computational complexity. In this way, a compromise is achieved between the complexity of the analyzed phenomena on the one hand and the model's practicability on the other. The proposed model has been experimentally verified using four IMs of different efficiency class and rotor cage material, all rated 1.5 kW. Besides enabling a quantitative insight into the impact of the stray load and iron losses on the operation of mains-supplied and vector-controlled IMs, the proposed model offers an opportunity to develop advanced vector control algorithms since vector control is based on the fundamental harmonic component of IM variables.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.195-204
• /
• 1996

We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.7
• /
• pp.20-29
• /
• 1998

As the packing density of ICs in recent submicron IC design increases, interconnects gain importance. Because interconnects directly affect on two major components of circuit performance, power dissipation and operating speed, circuit engineers are concerned with the optimal design of interconnects and the aid tool to design them. When circuit models of interconnects are given (including geometry and material information), the analysis process for the given structure is not an easy task, but conversely, it is much more difficult to design an interconnect structure with given circuit characteristics. This paper focuses on the latter process that has not been foucsed on much till now due to the complexity of the problem, and prsents a design aid tool(DATOIS) to synthesize interconnects. this tool stroes the circuit performance parameters for normalized interconnect geometries, and has two oeprational modes:analysis mode and synthesis mode. In the analysis mode, circuit performance parameters are obtained by searching the internal database for a given geometry and interpolates results if necessary . In thesynthesis mode, when a given circuit performance parameter satisfies a set of geometry condition in the database, those geometry structures are printed out.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.177-183
• /
• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.