• Title/Summary/Keyword: Circuit

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Anti-fuse program circuits for configuration of the programmable logic device

  • Kim, Phil-Jung;Gu, Dae-Sung;Jung, Rae-Sung;Park, Hyun-Yong;Kim, Jong-Bin
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.778-781
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    • 2002
  • In this paper, we designed the anti-fuse program circuit, and there are an anti-fuse program/sense/latch circuit, a negative voltage generator, power-up circuit and etc. in this circuit. An output voltage of a negative voltage generator is about -4,51V. We detected certainly it regardless of simulation result power rise time or temperature change to detect the anti-fuse program state of an anti-fuse program/sense/latch circuit and were able to know what performed a steady action. And as a result of having done a simulation while will change a resistance value voluntarily in order to check an anti-fuse resistance characteristic of this circuit oneself, it recognized as a programmed anti-fuse until 23k$\Omega$, and we were able to know that this circuit was a lot of margin than general anti-fuse resistance 500$\Omega$. Therefore, the anti-fuse program circuit of this study showed that was able to apply for configuration of the programmable logic device.

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Performance Characteristics of Thermoelectric Generator Modules For Parallel and Serial Electrical Circuits (전기회로 구성 방법에 따른 열전발전 모듈 성능 특성)

  • Kim, Yun-Ho;Kim, Myung-Kee;Kim, Seo-Young;Rhee, Gwang-Hoon;Um, Suk-Kee
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.22 no.5
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    • pp.259-267
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    • 2010
  • An experiment has been performed in order to investigate the characteristics of multiple thermoelectric modules (TEMs) with electrical circuits. The open circuit voltage of TEM connected parallel circuit is equal to the sum of individual TEMs. In contrast, the open circuit voltage is equal to the average of that individual TEM for a series circuit. The power output and conversion efficiency of TEM for both parallel and series circuits increase as the operating temperature conditions for individual TEMs becomes identical. Comparing parallel with series circuits, the power generation performance is more excellent for series circuit than parallel circuit. This result is attributed to the power loss from the TEM with better power generation performance.

Transient Fault Current Limiting Characteristics of a Transformer Type SFCL Using an Additional Magnetically Coupled Circuit

  • Lim, Seung-Taek;Lim, Sung-Hun
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.1
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    • pp.42-45
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    • 2017
  • In this paper, a transformer type SFCL (superconducting fault current limiter) using an additional magnetically coupled circuit was suggested. Its transient fault current limiting characteristics, due to the winding direction of additional coupled circuit, were analyzed through fault current limiting tests. The suggested transformer type SFCL was composed of the primary winding, and one secondary winding wound on the same iron core together with an additional magnetically coupled circuit. That circuit consists of the other secondary winding together with the other SC (superconducting) element connected in parallel with its other secondary winding. As one of the effective design parameters to affect the transient fault current of the SFCL, the fault current limiting tests of the suggested SFCL were carried out considering the winding direction of its additional coupled circuit. It was confirmed that, through the analysis on the fault current tests of the SFCL, the quench sequence of two SC elements comprising the suggested SFCL could be adjusted by the winding direction of the additional coupled circuit.

A Study on Current and Torque Characteristics Of Three-Phase Induction Motor in Single-Phase Operation. (삼상유도전동기의 결상시 전류 및 회전력특성에 관한 연구)

  • 유춘식;노창주
    • Journal of Advanced Marine Engineering and Technology
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    • v.6 no.1
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    • pp.25-33
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    • 1982
  • The characteristics of the stator current and torque of a small three- phase squirrel cage induction motor and studied experimentally under the situation of a single-phase operation due to various causes. Through the experiments, the torque-slip and current-slip curve of single-phase circuit as well as three-phase circuit are obtained and the needed constants are determined. The stator current and torque are calculated by the current and torque equations derived by the unbalanced circuit theory. The numerical values obtained from the above methods are compared with the experimental values under the same conditions. The results of the study are summerized as follow; 1) The values computed by the unbalanced circuit theory generally come to approach the values recorded through experiments. 2) Near the rated load, speed drop is less than 1.2 per cent of the speed of three-phase induction motor and torque reduces less than 3 per cent of it of three-phase induction motor when three-phase induction motor is run under a single-phase. On the other hand, the stator current in a single-phase circuit is more than 1.9 times of it in three-phase circuit. 3) The stalling torque in a single-phase circuit is reduced to about 41 per cent of it in three-phase circuit while the corresponding slip is moved toward the synchroneous speed and the corresponding stator current is increased.

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Practical Design and Implementation of a Power Factor Correction Valley-Fill Flyback Converter with Reduced DC Link Capacitor Volume (저감된 DC Link Capacitor 부피를 가지는 역률 개선 Valley-Fill Flyback 컨버터의 설계 및 구현)

  • Kim, Se-Min;Kang, Kyung-Soo;Kong, Sung-Jae;Yoo, Hye-Mi;Roh, Chung-Wook
    • The Transactions of the Korean Institute of Power Electronics
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    • v.22 no.4
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    • pp.277-284
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    • 2017
  • For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

An Electrical Repair Circuit for Yield Increment of High Density Memory (고집적 메모리의 yield 개선을 위한 전기적 구제회로)

  • 김필중;김종빈
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.4
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    • pp.273-279
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    • 2000
  • Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

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The Effects of Circuit Training on Abdominal Fat in Obesity Coed (운동에 따른 비만 여대생의 복부지방에 미치는 영향)

  • Song, Myung-Soo;No, Hyun-Jeung;Kim, Sang-Soo
    • PNF and Movement
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    • v.8 no.1
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    • pp.21-29
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    • 2010
  • Purpose : The purpose of this research is to examine the effects of circuit weight training and aerobic exercise on the bodily formation and abdominal fat area of obese female college students. Methods : The female college students whose BMI is over $25kg/m^2$ were divided into the circuit weight training group and the aerobic exercise group and circuit weight training and aerobic exercise were conducted on the respective group five times a week. Resultlts : 1. The tendency of statistically significant reduction in weight, body fat percentage, and BMI was shown in both the circuit weight training group and the aerobic exercise group but there were no significant differences between these groups. 2. The tendency of statistically significant reduction in total abdominal fat area, and subcutaneous fat area was shown in both the circuit weight training group and the aerobic exercise group but there were no significant differences between these groups. 3. Visceral fat area was reduced more in the aerobic exercise group than in the circuit weight training group Conclusion : It was confirmed that exercise alone in the state of no dietary treatment being given could cause obese people bodily formation.

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An IC Chip of a Cell-Network Type Circuit Constructed with 1-Dimensional Chaos Circuits

  • Eguchi, Kei;Ueno, Fumio;Zhu, Hongbing;Tobata, Toru;Ootani, Yuri
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.2000-2003
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    • 2002
  • In this paper, an IC chip of a cell- network type circuit constructed with 1-dimensional chaos circuits is reported. The circuit, is designed by sing switched-current (Sl) techniques. In the proposed circuit, by controlling connections of cells, an S- dimensional circuit (S = 1, 2, 3,…) and a synchronization system can be constructed easily. Furthermore, in spite of faults of a few cells, the circuit can reconstruct above-mentioned systems only to change connections of cells. This feature will open up new vista for engineering applications which are used in a distance place such as space, deep sea, etc. since it is difficult to repair faults of these application systems. To investigate the characteristics of the circuit, SPICE simulations are performed. The VLSI chip is fabricated from the layout design using a CAD tool, MAGIC. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

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A Study on Bead Height Control of GMAW by Short Circuit Time Ratio (단락시간비를 이용한 GMAW의 비드 높이 제어에 관한 연구)

  • 감병오;조상명;김상봉
    • Journal of Ocean Engineering and Technology
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    • v.16 no.2
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    • pp.53-59
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    • 2002
  • This paper shows the experimental results controlling the height of surface and back bead in GMAW by analyzing the unexpected gaps between base metals produced in welding and by controlling welding velocity due to the variation of the gap between base metals in thin-plate welding. The back bead behavior and burn-through in I-type butt joint $CO_2$ welding of thin mild steel are analyzed in the views of short circuit time ratio and short circuit frequency. It is shown through experimental consideration that the short circuit time ratio method is more reasonable than the short circuit frequency method in analyzing the formulation of back bead under changing the gap between base metals. Based on the these results, welding manipulator is designed so as to satisfy the bead height control in real time by measuring the short circuit time ratio. To show the effectiveness of the developed bead formulation control system, the experiment is implemented under two welding conditions such as increasing gap from 0mm to 0.8mm and gradually increasing gap from 0mm to 1.2mm. The experimental results show that the bead formulation can be controlled uniformly in spite of the variation of the gap between base metals.

A New Sustaining Driver for AC PDPs with Reduced Sustain Voltage by Half (새로운 유지구동전압 반감형 AC PDP 구동회로)

  • Lim, Seung-Bum;Cho, Pil-Yong;Chae, Soo-Yong;Kang, Kyoung-Woo;Yoo, Jong-Gul;Ko, Jong-Sun;Hong, Sonn-Chan
    • Proceedings of the KIPE Conference
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    • 2005.07a
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    • pp.452-455
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    • 2005
  • This paper proposes a new sustaining driver for AC PDP(Plasma Display Panel), which improves the performance of conventional circuit with reduced sustain voltage such as TERES(TEchnology of REciprocal Sustainer). In the TERES circuit, the sustain voltage is the half of general sustaining driver and there is no energy recovery circuit. The circuit proposed in his paper has an energy recovery circuit and removes surge currents. Although the energy recovery circuit is added, the number of active switching elements is the same as the TERES circuit. The operations of the proposed circuit are analyzed for each mode and its validity is verified by the simulations using PSpice program.

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