• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.402-407
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• 2008

Recent popularity in mobile electronics requires higher standard on the mechanical strength of electronic packaging. Thus, the method of soldering between chip and substrate in electronic packaging process is changing from conventional method using intermetallic compound to a new method using organic solderability preservative (OSP) in order to improve the stability and the reliability of final product. Since current organic solder preservatives have several serious problems like thermo-stability during packaging process, however, it is necessary to develop new OSPs having thermo-stability. The main purpose of this study is to investigate the effect of MeOH/IPA (Isopropyl alcohol) ratio on the fluxing of a new OSP, developed in previous research, andto find out an optimum formulation of flux components for the application of the OSP in current packaging process. As a result of this study, it was revealed that higher MeOH/IPA ratio in flux showed better performance of fluxing a new OSP.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.135-145
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• 2006

This paper presents the theory, design, fabrication and characterization of the novel low actuation voltage capacitive shunt RF-MEMS switch using a corrugated membrane with HRS MEMS packaging. Analytical analyses and experimental results have been carried out to derive algebraic expressions for the mechanical actuation mechanics of corrugated membrane for a low residual stress. It is shown that the residual stress of both types of corrugated and flat membranes can be modeled with the help of a mechanics theory. The residual stress in corrugated membranes is calculated using a geometrical model and is confirmed by finite element method(FEM) analysis and experimental results. The corrugated electrostatic actuated bridge is suspended over a concave structure of CPW, with sputtered nickel(Ni) as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon(HRS) substrate. The corrugated switch on concave structure requires lower actuation voltage than the flat switch on planar structure in various thickness bridges. The residual stress is very low by corrugating both ends of the bridge on concave structure. The residual stress of the bridge material and structure is critical to lower the actuation voltage. The Self-alignment HRS MEMS package of the RF-MEMS switch with a $15{\Omega}{\cdot}cm$ lightly-doped Si chip carrier also shows no parasitic leakage resonances and is verified as an effective packaging solution for the low cost and high performance coplanar MMICs.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.41-48
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• 2010

To improve the pot life of one-part in-house anisotropic conductive paste (ACP) formulations, 2-methyl imidazole curing accelerator powders were encapsulated with five agents. Through measuring the melting point of the five agents using DSC, it was confirmed that a encapsulation process with liquid-state agents is possible. Viscosity of ACP formulations containing the encapsulated imidazole powders was measured as a function of storage time from viscosity measurements. As a result, pot life of the formulations containing imidazole powders encapsulated with stearic acid and carnauba wax was improved, and these formulations indicated similar curing behaviors to a basic formulation containing rare imidazole. However, the bondlines made of these formulations exhibited low average shear strength values of about 37% level in comparison with the basic formulation.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.49-53
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• 2018

Recently, technologies for integrating various devices such as a flexible device, a transparent device, and a MEMS device have been developed. The key processes of heterogeneous device manufacturing technology are chip or wafer-level bonding process, substrate grinding process, and thin substrate handling process. In this study, the effect of Si substrate grinding process on the electrical properties of tin oxide thin films applied as transparent thin film transistor or flexible electrode material was investigated. As the Si substrate thickness became thinner, the Si d-spacing decreased and strains occurred in the Si lattice. Also, as the Si substrate thickness became thinner, the electric conductivity of tin oxide thin film decreased due to the lower carrier concentration. In the case of the thinner tin oxide thin film, the electrical conductivity was lower than that of the thicker tin oxide thin film and did not change much by the thickness of Si substrate.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.71-77
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• 2011

Main parameters of the screen printing were determined and the printing parameters were optimized for 0402, 0603, and 1005 chips in this study. The solder pastes used in this study were Sn-3.0Ag-0.5Cu and Sn-0.7Cu. The process parameters were stencil thickness, squeegee angle, printing speed, stencil separating speed and gap between stencil and PCB. The printing pressure was fixed at 2 $kgf/cm^2$. From ANOVA results, the stencil thickness and the squeegee angle were determined to be main parameters for the printing efficiency. The printing efficiency was optimized with varying two main parameters, the stencil thickness and the squeegee angle. The printing efficiency increased as the squeegee angle was lowered under 45o for all chips. For the 0402 and the 0603 chips, the printing efficiency increased as the stencil thickness decreased. On the other hand, for the 1005 chip, the printing efficiency increased as the stencil thickness increased.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.