• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.159-163
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• 2002

So far, many kinds of researches on the chip components and MCM-C RF module especially on the 3-dimensional ceramic module using embedded passives have been performed. LTCC system has many kinds of advantages, like low loss, low cost of process, stability of process etc..The electrical behaviors of components are affected by that of the material systems including dielectrics and conductors. In this study, many kinds of conductor pastes in the variation with metal content and grain size are fabricated and their effect on the characteristics of stripline resonator are examined upto 6 ㎓.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.175-182
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• 2017

In light emitting diode (LED) chip packaging, wire bonding is an important process that connects the LED chip on the lead frame pad with the Au wire and enables electrical operation for the next process. The wire bonding process is divided by two types: thermo compression bonding and ultrasonic bonding. Generally, the wire bonding process consists of three steps: 1st ball bonding that bonds the shape of the ball on the LED chip electrode, looping process that hangs the wire toward another connecting part with a loop shape, and 2nd stitch bonding that forms and bonds to another electrode. This study analyzed the factors affecting the LED die bonding processes to optimize the process capability that bonds a small Zener diode chip on the PLCC (plastic-leaded chip-carrier) LED package frame, and then applied response surface analysis. The design of experiment (DOE) was established considering the five factors, three levels, and four responses by analyzing the factors. As a result, the optimal conditions that meet all the response targets can be derived.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.9-15
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• 2021

Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (R_q) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.10
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• pp.876-882
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• 2018

The purpose of this research is to verify the feasibility of Plastic Ball Grid Array (PBGA), one of the most popular chip packaging types for commercial electronics, under strong random vibration occurred in satellite during launch. Experiment were performed by preparing daisy chained PCB specimen, where large size PBGA were surface mounted, and the PCB was fixed to an aluminum frame which is commonly used to install the electronics parts to satellite. Then the entire sample was fixed to vibration tester. The random vibration power spectrum density employed in the tests were composed of two steps, the acceptance level of 22.7 Grms, and qualification level of 32.1 Grms with given period of time. The test results showed no solder cracks, which provided the strong structural integrity and feasibility evidences of the PBGA packaging to aerospace electronics. Numerical analyses were also performed to calculate the solder stresses and analyze their development mechanism.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.7-11
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• 2013

As thermosonic ball bonding is developed for more and more advanced applications in the electronic packaging industry, the control of process stresses induced on the integrated circuits becomes more important. If Cu bonding wire is used instead of Au wire, larger ultrasonic levels are common during bonding. For advanced microchips the use of Cu based wire is risky because the ultrasonic stresses can cause chip damage. This risk needs to be managed by e.g. the use of ultrasound during the impact stage of the ball on the pad ("pre-bleed") as it can reduce the strain hardening effect, which leads to a softer deformed ball that can be bonded with less ultrasound. To find the best profiles of ultrasound during impact, a numerical model is reported for ultrasonic bonding with capillary dynamics combined with a geometrical model describing ball deformation based on volume conservation and stress balance. This leads to an efficient procedure of ball bond modelling bypassing plasticity and contact pairs. The ultrasonic force and average stress at the bond zone are extracted from the numerical experiments for a $50{\mu}m$ diameter free air ball deformed by a capillary with a hole diameter of $35{\mu}m$ at the tip, a chamfer diameter of $51{\mu}m$, a chamfer angle of $90^{\circ}$, and a face angle of $1^{\circ}$. An upper limit of the ultrasonic amplitude during impact is derived below which the ultrasonic shear stress at the interface is not higher than 120 MPa, which can be recommended for low stress bonding.

• Applied Chemistry for Engineering
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• v.8 no.3
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• pp.533-542
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• 1997

Due to the trends of faster and denser circuit design, dielectric properties of packaging materials for semiconductor will give a greater influence on performance and reliability. Also as chip becomes more densified, thermal dissipation becomes a critical reliability issue. Consequently, four important properties for manufacturing semiconductor packaging materials are low values of dielectric constant, high values of thermal conductivity, relatively low values of thermal expansion coefficient and low cost. Thus, in this study, to achieve increased performance of EMC, crystalline silica was selected as the filler for epoxy matrix. As a result, when the volume percent of crystal silica was 60~70%, good properties as packaging materials for semiconductor were achieved. In addition, overall molding condition of EMC in this experiment was established.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.7-18
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• 2008

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.13-18
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• 2000

Low temperature co-fired ceramics on metal (LTCC-M) is efficient for embedding passive components with good tolerance in a module due to the dimensional stability in x and y directions by the constraint of metal core during the firing. In addition, the radiation noise can be reduced by metal core. In this paper, embedded passive components were introduced and a power amplifier module (PAM) fabricated by using the passive components was explained. The embedded passive components in test patters showed the tolerance of 10~20% and the good repeatability in tolerance of embedded passives was maintained in module fabrication. The shortened traces in multi chip modules (MCMs) make the signal delay time decreased and the embedded passives simplify the packaging processes owing to the less solder points, which enhance the electrical performance and increase the reliability of the modules. The LTCC-M technology is one of the promising candidates for RF application and is expected to expand its applications to power and high performance devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.84-87
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• 2003

Since Pb-free solder alloys have been used extensively in microelectronic packaging industry, the interaction between UBM (Under Bump Metallurgy) and solder is a critical issue because IMC (Intermetallic Compound) at the interface is critical for the adhesion of mechanical and the electrical contact for flip chip bonding. IMC growth must be fast during the reflow process to form stable IMC. Too fast IMC growth, however, is undesirable because it causes the dewetting of UBM and the unstable mechanical stability of thick IMC. UP to now. Ni and Cu are the most popular UBMs because electroplating is lower cost process than thin film deposition in vacuum for Al/Ni(V)/Cu or phased Cr-Cu. The consumption rate and the growth rate of IMC on Ni are lower than those of Cu. In contrast, the wetting of solder bumps on Cu is better than Ni. In addition, the residual stress of Cu is lower than that of Ni. Therefore, the alloy of Cu and Ni could be used as optimum UBM with both advantages of Ni and Cu. In this paper, the interfacial reactions of Sn-3.5Ag-0.7Cu solder on Ni-xCu alloy UBMs were investigated. The UBMs of Ni-Cu alloy were made on Si wafer. Thin Cr film and Cu film were used as adhesion layer and electroplating seed layer, respectively. And then, the solderable layer, Ni-Cu alloy, was deposited on the seed layer by electroplating. The UBM consumption rate and intermetallic growth on Ni-Cu alloy were studied as a function of time and Cu contents. And the IMCs between solder and UBM were analyzed with SEM, EDS, and TEM.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.43-49
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• 2007

Thickness of intermetallic compounds and consumption rates of under bump metallurgies (UBMs) were investigated in wafer-level solder bumping with variations of UBM materials and reflow times. In the case of Cu UBM, $0.6\;{\mu}m-thick$ intermetallic compound layer was formed before reflow of Sn solder, and the average thickness of the intermetallic compound layer increased to $4\;{\mu}m$ by reflowing at $250^{\circ}C$ for 450 sec. On the contrary, the intermetallic layer had a thickness of $0.2\;{\mu}m$ on Ni UBM before reflow and it grew to $1.7\;{\mu}m$ thickness with reflowing for 450 sec. While the consumption rates of Cu UBM were 100nm/sec fur 15-sec reflow and 4.50-sec for 450-sec reflow, those of Ni UBM decreased to 28.7 nm/sec for 15-sec reflow and 1.82 nm/sec for 450-sec reflow.