• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.33-38
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• 2013

In this study, both a finite element analysis and an experimental analysis are executed to investigate the mechanical characteristics of dielectric material effects on warpage. Also, viscoelastic material properties are measured by DMA and are considered in warpage simulation. A finite element analysis is done by using both thermal elastic analysis and a thermo-viscoelastic analysis to predict the nonlinear effects. For experimental study, specimens warpage of non-symmetric structure with body size of $22.5{\times}22.5$ mm, $37.5{\times}37.5$ mm and $42.5{\times}42.5$ mm are measured under the reflow temperature condition. From the analysis results, experimental warpage is not similar to FEA results using thermal elastic analysis but similar to FEA results using thermo-viscoelastic analysis. Also, its effect on substrate warpage is increased as core thickness is decreased and body size is getting larger. These FEA and the experimental results show that the nonlinear characteristics of dielectric material play an important role on substrate warpage. Therefore, it is strongly recommended that non-linear behavior characteristics of a dielectric material should be considered to control warpage of FCBGA substrate under conditions of geometry, structure and manufacturing process and so on.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.65-68
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• 2013

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.205-207
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• 2003

In this paper, we propose novel, small and integrated microwave chip filter using high dielectric substrates. A variety of dielectric substrates can be selected for the specifications of products according to dielectric, Q-factors, temperature stability ect. This paper describes an application of the very high dielectric constant (K=133) substrate for design of a band pass filter to a 5.8GHz Transmitter/receiver(T/R) module.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.1-6
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• 2014

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.552-554
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• 1995

In long-haul high speed optical communications, the distance between a transmitter and a receiver depends on the amount of light coupled to a single mode optical fiber from the laser diode(LD) as well as the LD characteristic itself. And the transmitter module must have long lifetime. high reliability, and even simple structure. Such points have induced laser welding technique to be a first choice in opto-electronic module packaging because it can provide strong weld joint in a short time with very small coupling loss. In this paper, packaging considerations and characteristics for high speed LD modules are discussed. They include optical path design factors for larger aligning tolerance, and novel laser welding processes for component assembly. For low coupling loss after laser welding processes, the optical path for optimum coupling of a single mode optical fiber into the LD chip was designed with the GRIN lens system providing sufficiently large aligning tolerance both in the radial and axial directions. The measured sensitivity of the LD module was better than -33.7dBm(back to back) at a BER of $10^{-10}$ with a 2.5Gbps NRZ $2^{23}-1$ PRBS.

• Journal of the Optical Society of Korea
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• v.13 no.4
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• pp.434-438
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• 2009

In this paper, a 12.5-Gb/s optical transmitter is implemented using 0.13-${\mu}m$ CMOS technology. The optical transmitter that we constructed compensates temperature effects of VCSEL (Vertical cavity surface emitting laser) using auto-power control (APC) and auto-modulation control (AMC). An external monitoring photodiode (MPD) detects optical power and modulation. The proposed APC and AMC demonstrate 5$\sim$20-mA of bias-current control and 5$\sim$20-mA of modulation-current control, respectively. To enhance the bandwidth of the optical transmitter, an active feedback amplifier with negative capacitance compensation is exploited. The whole chip consumes only 140.4-mW of DC power at a single 1.8-V supply under the maximum modulation and bias currents, and occupies the area of 1280-${\mu}m$ by 330-${\mu}m$ excluding bonding pads.

• Transactions on Electrical and Electronic Materials
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• v.10 no.3
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• pp.71-74
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• 2009

Electroplated Cu is a cost efficient metallization method in microelectronic packaging applications. Typically in 3-D chip staking technology, utilizing through silicon via (TSV), electroplated Cu metallization is inevitable for the throughput as well as reducing the cost of ownership (COO).To achieve a comparable film quality to sputtering or CVD, a pre-cleaning process as well as plating process is crucial. In this research, atmospheric plasma is employed to reduce the usage of chemicals, such as trichloroethylene (TCE) and sodium hydroxide (NaHO), by substituting the chemical assisted organic cleaning process with plasma surface treatment for Cu electroplating. By employing atmospheric plasma treatment, marginally acceptable electroplating and cleaning results are achieved without the use of hazardous chemicals. The experimental results show that the substitution of the chemical process with plasma treatment is plausible from an environmentally friendly aspect. In addition, plasma treatment on immersion Sn/Cu was also performed to find out the solderability of plasma treated Sn/Cu for practical industrial applications.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.