• Title/Summary/Keyword: Chip pattern

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Development of DNA Chip Microarray by Using Secondary-step immobilization methods (2단계 고정화법을 이용한 DNA칩 마이크로어레이의 개발)

  • Yoon, Hee-Chan;Kim, Do-Kyun;Shin, Hoon-Kyu;Kwon, Young-Soo
    • Proceedings of the KIEE Conference
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    • 2002.11a
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    • pp.263-265
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    • 2002
  • We have used the secondary-step immobilization methods based on the chip pattern of hydrophobic self-assembly layers to assemble microfabricated particles onto the chip pattern. Immobilization of DNA, fabrication of the particles and the chip pattern, arrangement of the particles on the chip pattern, and recognition of each using DNA fluorescence measurement were carried out. Establishing the walls, the arrangement stability of the particles was improved. Each DNA is able to distinguish by using the lithography process on the particles. Advantages of this method are process simplicity, wide applicability and stability. It is thought that this method can be applicable as a new fabrication technology to develop a minute integration type biosensor microarray.

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Design and Implementation of Parabolic Speed Pattern Generation Pulse Motor Control Chip (포물선 가감속 패턴을 가지는 정밀 펄스 모터 콘트롤러 칩의 설계 및 제작)

  • Won, Jong-Baek;Choi, Sung-Hyuk;Kim, Jong-Eun;Park, Jone-Sik
    • Proceedings of the KIEE Conference
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    • 2001.11c
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    • pp.284-287
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    • 2001
  • In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

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A Study on PWM Pattern for Driving Induction Motor using ${\mu}$-Processor and One Chip (범용 ${\mu}$-Processor와 One Chip으로 구현되는 유도전동기 구동 PWM Pattern에 관한 연구)

  • Hwang, Y.M.;Hoe, T.W.;Park, J.H.;Shin, D.R.;Cho, Y.G.;Woo, J.I.
    • Proceedings of the KIEE Conference
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    • 1998.11a
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    • pp.179-181
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    • 1998
  • In this paper, one chip PWM pattern generator which eliminates time delay of computations and improves utilization factor of voltage is proposed. Both amplitude of sinusoidal signal and triangular signal are directly controlled. Thus, time delay of computations can be eliminated, and it is possible to track accurately instantaneous current for a sudden change of load with microprocessor 80C196KC. In addition, setting dead-time is also possible for wide range. From experimental work with inverter system for driving induction motor, the validity of proposed one chip PWM pattern generator is verified.

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Development of DNA Chip Microarray Using Hydrophobic Template (소수성 Template를 이용한 DNA Chip Microarray의 개발)

  • Choi, Yong-Sung;Park, Dae-Hee
    • Proceedings of the KIEE Conference
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    • 2004.11a
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    • pp.271-274
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    • 2004
  • Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarray was made by immobilizing many kinds of biomaterials on transducers (particles). DNA chip microarray was prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of m-scale sites. The particles occupied a different sites from site to site. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using a hydrophobic interaction for assembly.

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Appropriate Package Structure to Improve Reliability of IC Pattern in Memory Devices (메모리 반도체 회로 손상의 예방을 위한 패키지 구조 개선에 관한 연구)

  • 이성민
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.32-35
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    • 2002
  • The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

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Global Coordinate Extraction of IC Chip Pattern Using Form Matching (형태정합을 이용한 집적회로 패턴의 전체좌표 추출)

  • Ahn, Hyun-Sik;Cho, Seok-Je;Lee, Chul-Dong;Ha, Yeong-Ho
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.4
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    • pp.120-126
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    • 1989
  • IC chip layout pattern recognition algorithms using image processing techniques are being developed for the automation of manufacturing and inspecting chips. Recognitioin of chip pattern requires feature extraction from nach rrame of chip image adn needs to match the feature data through all frames. In this paper, vertex position and form having layout information are extracted by the feature straightening algorithm, and global coordinates of layout pattern are extracted by the feature straightening algorithm, and global coordinates of layout pattern are obtainnd by vertex form matching from the overlapped area of neighbour frame.

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Pattern Classification Algorithm of DNA Chip Image using ANN (신경망을 이용한 DNA칩 영상 패턴 분류 알고리즘)

  • Joo, Jong-Tae;Kim, Dae-Wook;Sim, Kwee-Bo
    • Journal of the Korean Institute of Intelligent Systems
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    • v.16 no.5
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    • pp.556-561
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    • 2006
  • It is very important to classify the DNA Chip image pattern in order to acquire useful information about genetic disease of people. In this paper, we developed the novel pattern classification method of DNA Chip image using MLP based back-propagation and Self organizing Map learning algorithm. And then we compared and analyzed these classified pattern results. Also we carried out experiment in the MV2440 board using CPU Cote for S3C2440(ARM 920T) and PC environment, and displayed its results in order to give the genetic information to user mote easily in various environment.

Fabrication of DNA Chip Using a Hydrophobic Template (소수성 Template를 이용한 DNA칩의 제작)

  • Choi, Yong-Sung;Moon, Jong-Dae;Lee, Kyung-Sup
    • Proceedings of the KIEE Conference
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    • 2006.07c
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    • pp.1315-1316
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    • 2006
  • Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarray was made by immobilizing many kinds of biomaterials on transducers (particles). DNA chip microarray was prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of m-scale sites. The particles occupied a different sites from site to site. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using a hydrophobic interaction for assembly.

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Vibration Reduction of Chip-Mount System (칩 마운트 시스템의 진동 경감)

  • 임경화;장헌탁
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.11 no.8
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    • pp.331-337
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    • 2001
  • The purpose of this study is to analyze the principal causes of vibration problem and find out the method of vibration reduction in a chip-mount system. The principal causes are investigated through measurements of vibration spectrum and model parameters. Modal parameters are obtained by using an experimental model test. Based on the model parameters from experiments. a model of finite element method is formulated. The model presents effective redesign of increasing the natural frequencies in order to reduce the vibration of a chip-mount system. Further, through computer simulation for the behavior of head to be main vibration source, the best acceleration pattern of head movement can be verified to achieve effective head-positioning and reduce the vibration due to head movement.

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Chip Shape Control using AE Signal in Pure Copper Turning (순동선삭가공에서 AE 신호를 이용한 칩 형상 제어)

  • Oh, Jeong Kyu;Kim, Pyeong Ho;Koo, Joon Young;Kim, Duck Whan;Kim, Jeong Suk
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.23 no.4
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    • pp.330-336
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    • 2014
  • The continuous chip generated in cutting process deteriorates workpiece, tool, and machine tool system. It is necessary to treat this continuous chip in ductile material machining condition for stable cutting. This paper deals with the chip control method using acoustic emission(AE) signal in pure copper turning operation. AE raw signals, root mean square(RMS) signals and wavelet transformed signals measured in turning process are introduced to analysis for chip patterns. With analysis of AE signals, it is obtained that the produced chip patterns are correlated with the specified AE signals which are transformed by fuzzy pattern algorithm. By this experimental investigation, the chip patterns can be classified at significant level in pure copper machining process and controlled from continuous chips to reduced-length stable chips.