• 제목/요약/키워드: Chip on chip technology

검색결과 1,651건 처리시간 0.03초

Comparisons of Interfacial Reaction Characteristics on Flip Chip Package with Cu Column BOL Enhanced Process (fcCuBE®) and Bond on Capture Pad (BOC) under Electrical Current Stressing

  • Kim, Jae Myeong;Ahn, Billy;Ouyang, Eric;Park, Susan;Lee, Yong Taek;Kim, Gwang
    • 마이크로전자및패키징학회지
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    • 제20권4호
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    • pp.53-58
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    • 2013
  • An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

A Bus Data Compression Method on a Phase-Based On-Chip Bus

  • Lee, Jae-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권2호
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    • pp.117-126
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    • 2012
  • This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

5축 FMS라인의 절삭 칩 처리를 위한 칩 회수처리장치 시뮬레이션에 관한 연구 (A Study on Simulation of Chip Recycling System for the Management of Cutting Chip in 5-Axis FMS Line)

  • 이인수;김해지;김덕현;김남경
    • 한국기계가공학회지
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    • 제12권6호
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    • pp.175-181
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    • 2013
  • The primary element of machining automation is to maximize the utilization of machine tools, which determines the output and lead-time. In particular, 95% of raw materials for wing ribs are cut into chips and 0.6 ton of chips are generated every hour from each machine tool. In order to verify the chip recycling system that controls the chips from the machines in five-axis FMS line, a simulation of the virtual model is constructed using the QUEST simulation program. The optimum speed of the chip conveyor and its operating conditions that directly affect the efficiency of the FMS line are presented including the chip conveyor speed, the maximum capacity of the hopper, and the number of chip compressors.

Design of a New ISFET Array Chip

  • Yeow, Terence;Seo, Hwa-Il;Mulcahy, Dennis;Haskard, Malcolm
    • 센서학회지
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    • 제4권4호
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    • pp.55-61
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    • 1995
  • 가변 입력전압을 이용하여 ISFET의 문턱전압을 검출하는 새로운 개념의 ISFET array chip을 설계하였다. 설계된 칩은 240개의 pH-ISFET와 신호처리회로를 포함하며, 증가된 신뢰성 및 정확성, 디지탈 출력 그리고 멀티센서로의 응용성 등의 특성을 가진다. 칩제조를 위해 CMOS 공정을 응용한 새로운 공정을 설계하였고 칩을 layout 하였다.

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Nanoscale Fabrication of Biomolecular Layer and Its Application to Biodevices

  • Park, Jeong-Woo;Nam, Yun-Suk;Masamichi Fujihira
    • Biotechnology and Bioprocess Engineering:BBE
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    • 제9권2호
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    • pp.76-85
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    • 2004
  • Biodevices composed of biomolecular layer have been developed in various fields such as medical diagnosis, pharmaceutical screening, electronic device, photonic device, environmental pollution detection device, and etc. The biomolecules such as protein, DNA and pigment, and cells have been used to construct the biodevices such as biomolecular diode, biostorage device, bioelectroluminescence device, protein chip, DNA chip, and cell chip. Substantial interest has focused upon thin film fabrication or the formation of biomaterials mono- or multi-layers on the solid surfaces to construct the biodevices. Based on the development of nanotechnology, nanoscale fabrication technology for biofilm has been emerged and applied to biodevices due to the various advantages such as high density immobilization and orientation control of immoblized biomolecules. This review described the nanoscale fabrication of biomolecular film and its application to bioelectronic devices and biochips.

Determination of stress state in formation zone by central slip-line field chip

  • Toropov Andrey;Ko Sung Lim
    • International Journal of Precision Engineering and Manufacturing
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    • 제6권3호
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    • pp.24-28
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    • 2005
  • Stress state of chip formation zone is one of the main problems in metal cutting mechanics. In two-dimensional case this process is usually considered as consistent shears of work material along one of several shear surfaces, separating chip from workpiece. These shear planes are assumed to be trajectories of maximum shear stress forming corresponding slip-line field. This paper suggests a new approach to the constriction of slip-line field, which implies uniform compression in chip formation zone. Based on the given model it has been found that imaginary shear line in orthogonal cutting is close to the trajectory of maximum normal stress and the problem about its determination has been considered as well. It has been shown that there is a second central slip-line field inside chip, which corresponds well to experimental data about stress distribution on tool rake face and tool-chip contact length. The suggested model would be useful in understanding mechanistic problems in machining.

비수식화 바이오칩 및 유전자 검출 (Genome Detection Using an DNA Chip Array and Non-labeling DNA)

  • 최용성;이경섭
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.402-403
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    • 2006
  • This research aims to develop the multiple channel electrochemical DNA chip using microfabrication technology. At first, we fabricated a high integration type DNA chip array by lithography technology. Several probe DNAs consisting of thiol group at their 5-end were immobilized on the gold electrodes. Then target DNAs were hybridized and reacted. Cyclic voltammetry showed a difference between target DNA and control DNA in the anodic peak current values. Therefore, it is able to detect a plural genes electrochemically after immobilization of a plural probe DNA and hybridization of non-labeling target DNA on the electrodes simultaneously. It suggested that this DNA chip could recognize the sequence specific genes.

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RF 응용을 위한 플립칩 기술 (Overview on Flip Chip Technology for RF Application)

  • 이영민
    • 마이크로전자및패키징학회지
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    • 제6권4호
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    • pp.61-71
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    • 1999
  • 통신분야에서 사용주파수대역의 증가, 제품의 소형화 및 가격경쟁력등의 요구에 따라 RF 소자의 패키징 기술도 플라스틱 패키지 대신에 flip chip interconnection, MCM(multichip module)등과 같은 고밀도 실장기술이 발전해가고 있다. 따라서, 본 논문은 최근 수년간 보고된 응용사례를 중심으로 RF flip chip의 기술적인 개발방향과 장점들을 분석하였고, RF 소자 및 시스템의 개발단계에 따른 적합한 적용기술을 제시하였다. RF flip chip의 기술동향을 요약하면, 1) RF chip배선은 microstrip 대신에 CPW 구조을 선택하며, 2) wafer back-side grinding을 하지 않아서 제조공정이 단순하고 wafer 파손이 적어 제조비용을 낮출 수 있고, 3) wire bonding 패키징에 비해 전기적인 특성이 우수하고 고집적의 송수신 모듈개발에 적합하다는 것이다. 그러나, CPW 배선구조의 RF flip chip 특성에 대한 충분한 연구가 필요하며 RF flip chip의 초기 개발 단계에서 flip chip interconnection 방법으로는 Au stud bump bonding이 적합할 것으로 제안한다.

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