• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.29-33
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• 2002

In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.3
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• pp.48-54
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• 2000

In this study the characteristics of chip formation of the cold drawn Bi-S free machining steels were assessed. And for comparison those of the cold drawn Pb-S free machining steel the hot rolled low carbon steel which has MnS as free machining inclusions and the conventional steels were also investigated. During chip formation the cold drawn free machining steels show relatively little change in thickness and width of chip compare to those of the conventional carbon steels. And a single parameter which indicates the degree of deformation during chip formation chip cross-section area ratio is introduced. The chip cross-section area ratio is defined as chip cross-section area is divided by undeformed chip cross-section area. The variational patters of the chip cross-section area ratio of the materials cut are similar to those of the shear strain values. The shear stress however seems to be dependent on the carbon content of the materials. The cold drawn Bi-S and Pb-S steels show nearly the same chip forming behaviors and the energy consumed during chip formation is almost same. A low carbon steel without free machining aids shows poor chip breakability due to its high ductility. By introducing a small amount of free machining inclusions such as MnS Bi, Pb or merely increasing carbon content the chip breakability improves significantly.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.2
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• pp.96-101
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• 2000

In machining with cutting tool inserts having complex chip groove shape the flow curl and breaking pattern of the chip are different than in flat-face inserts. In the present work an effort is made to understand the three basic phe-nomena occurring in a chip since its formation in machining with groove type and pattern type inserts. These are the ini-tial chip flow the subsequent development of up and side curl and the final chip breaking due to the development of tor-sional and bending stresses. in this paper chip flow angle in a groove type and pattern type inserts. The expres-sion for chip flow angle in groove type and pattern type inserts is also verified experimentally using high speed filming techniques.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.7 no.3
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• pp.118-125
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• 1998

Chip control is a major problem in automatic machining process, especially in finish turning operation. In this case, chip breaker is one of the important factors to be determined. As unbroken chips are grown. these deteriorate the surface roughness. and proces automation can not be carried out. In this study to get rid of chip curling problem while turning internal hole. optimal chip breaker is selected from the experiment. The experiment is planned with Taguchi's method that is based on the orthogonal arrary of design factors. From the response table. cutting speed, feedrate, depth of cut and tool geometry turn to be major factors affecting chip formation. Then, optimal chip breaker is selected. and this is verified as good enough for chip control from the experiment.

• Journal of Mechanical Science and Technology
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• v.14 no.9
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• pp.997-1004
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• 2000

The experiments were conducted by using water and paraffin slurry to investigate the effect of a chip spacing in the multichip module on the cooling characteristics from an in-line $4{\times}3$ array of discrete heat sources which were flush mounted on the top wall of a channel. The experimental parameters were chip spacing in a multichip module, heat flux of simulated VLSI chip, mass fraction of paraffin slurry, and channel Reynolds number. The removable heat flux at the same chip surface temperature decreased as the chip spacing decreased at the first and fourth rows. The local heat transfer coefficients for the paraffin slurry were larger than those for water, and the chip spacing on the local heat transfer coefficients for paraffin slurry influenced less than that for water. The enhancement factor for paraffin slurry showed the largest value at a mass fraction of 5% regardless of the chip spacing, and the enhancement factors increased as the chip spacing decreased. This means that the paraffin slurry is more effective than water for cooling of the highly integrated multichip module.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.481-485
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• 1987

The fabrication of a micro mass flow sensor on a silicon chip by means of micro-machining technology is described on this paper. The operation of micro mass flow sensor is based on the heat transfer from a heated chip to a fluid. The temperature differences on the chip is a measure for the flow velocity in a plane parallel with the chip surface. An anisotropic etching technigue was used for the formation of the V-type groove in this fabrication. The micro mass flow sensor is made up of two main parts ; A thin glass plate embodying the connecting parts and mass flow sensor parts in silicon chip. This sensor have a very small size and a neglible dead space. Micro mass flow sensor can fabricate on silicon chip by micro machining technology too.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.5
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• pp.559-563
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• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• Journal of the Korean Wood Science and Technology
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• v.29 no.3
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• pp.68-72
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• 2001

In order to effectively use the waste wood, two types of woodceramics chip tile were made from woodceramics chip, gravel, zeolite and additions. The woodceramics chip was made from branch of apple tree (Malus pumila Mill.) Snow melting property, bending strength and compressive strength of woodceramics chip tile were tested according to the mixing rate of woodceramics chip. Snow melting properties of woodceramics chip tile increased after additions treatment but mechanical properties were reduced significantly after additions treatment. The results indicate that the additions are effective for snow melting property but negative effect on mechanical properties.