• Applied Biological Chemistry
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• v.30 no.1
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• pp.65-70
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• 1987

In Girder to measure the pressure and weight decrease of drying sample during the vacuum drying process of food, sensing devices were designed and constructed with strain gauge. Microcomputer based vacuum drying system was made up of these devices interfaced to apple II microcomputer. The electrical output signal from vacuum sensor which constituted with Bourdon tube whereon strain gauge attached were digitalized and input to microcomputer through the MC 6821 interface I.C. chip. The relationship between read-out digital value (D) from microcomputer and readings of vacuum gauge (P, mmHg) was P=-146.136+3.620D'(r=0.9994) The pressure control of vacuum dryer was successfully conducted in the range of $400{\sim}600\;mmHg$ accuracy. The digitalized load cell output (D) could be correlated with the real weight (W, g) as W=-14,000+0.585D (r=0.9998) Drying curves of green red pepper under $64^{\circ}C$, $400{\sim}600\;mmHg$ was similar to those of red pepper and differently affected by the degree of vacuum pressure but was varied according to their shape (cut or whole). Moisture movement of green red pepper during the vacuum drying process was fitted to Page model. The empirical equations obtained were $M-M_e/M_o-M_e={\exp}\;(-0.0673{\theta}^{1.177})$ and $M-M_e/M_o-M_e={\exp}\;(-0.0655\;{\theta}^{1.477})$ for whole and cut green red pepper, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.47-55
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• 2010

The power line communication channel has characteristic variation problems which are caused by load. The spread spectrum technique has been used to overcome these problems. One of that is the direct sequence spread spectrum(DS/SS) system which is not necessary to additional hardwares. The BER of DS/SS system is decreased by longer length of PN code, but data transfer rate is decreases, so data transfer rate is hard to satisfies their own specifications especially in narrowband PLC systems. Spread Spectrum system with Dual-processing Gain tries to reflect cyclic characteristics of power line noise. But that system assumes that shapes of power line channel are symmetrical with respect to the 1/4 point of main frequency(60Hz in Korea), therefore cannot achieves various shapes of real power line noise. Thus in this paper, noise adaptive DS/SS system which PN code is changed by noise levels for various channel noises is proposed and simulated. The different kinds of noises are modeled and measured for simulation, the proposed system is verified that has lower data transfer rate and lower error rate than conventional system by simulation results.

• Korean Journal of Materials Research
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• v.10 no.12
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• pp.853-863
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• 2000

In this study, a new UBM materials system for solder flip chip interconnection of Cu pads were investigated using electroless copper (E-Cu) and electroless nickel (E-Ni) plating method. The interfacial reaction between several UBM structures and Sn-36Pb-2Ag solder and its effect on solder bump joint mechanical reliability were investigated to optimife the UBM materials design for solder bump on Cu pads. Fer the E-Cu UBM, continuous coarse scallop-like $Cu_{6}$ $Sn_{5}$ , intermetallic compound (IMC) was formed at the solder/E-Cu interface, and bump fracture occurred this interface under relative small load. In contrast, Fer the E-Ni/E-Cu UBM, it was observed that E-Ni effectively limited the growth of IMC at the interface, and the Polygonal $Ni_3$$Sn_4$ IMC was formed because of crystallographic mismatch between monoclinic $Ni_3$$Sn_4$ and amorphous E-Ni phase. Consequently, relatively higher bump adhesion strength was observed at E-Ni/E-Cu UBM than E-Cu UBM. As a result, it was fecund that E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on CU PadS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2601-2606
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• 2012

In this paper, an electricity management system, which saves energy by utilizing electricity consumption of load from an environment that uses at least two compact generators, is proposed and developed. A hardware is constructed by using TMS320C6713 DSP chip made by TI that is capable of high speed hardware floating point processing while serial communication is used for communication with a monitoring PC. Manual control is made possible from the monitoring PC and automatic on/off is enabled in the generator by using data collected by CT/PT sensor from the DSP mainboard. Test results confirm that the electricity management system proposed in this study functions without abnormality. The application of an algorithm that saves energy by using electricity consumption of load also allows for a longer supply of electricity compared to continuously using two compact generators.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1673-1681
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• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.219-225
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• 2014

This paper describes an IC for Power Factor Correction. It can use electrical appliances which convert power from AC to DC. The power factor can be influenced not only phase difference of voltage and current but also sudden change of current waveform. This circuit enables current wave supplied to load by close to sinusoidal and minimum phase difference of voltage and current waveform. A self oscillated 10[kHz]~100[kHz] pulse signal converted to PWM waveform and it chops rectified full wave AC power which flows to load device. The multiplier and zero current detector circuit, UVLO, OVP, BGR circuits were designed. This IC has been designed and whole chip simulation use 0.5[um] double poly, double metal 20[V] CMOS process.

• Journal of IKEEE
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• v.24 no.2
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• pp.559-569
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• 2020

One of the deep-running algorithms, CNN's artificial intelligence application uses off-chip memory to store data on the Convolution Layer. DMA can reduce processor load at every data transfer. It can also reduce application performance degradation by varying the order in which data from the Convolution layer is transmitted to the global buffer of the accelerator. For basic layouts with continuous memory addresses, SG-DMA showed about 3.4 times performance improvement in pre-setting DMA compared to using ordinaly DMA, and for Ideal layouts with discontinuous memory addresses, the ordinal DMA was about 1396 cycles faster than SG-DMA. Experiments have shown that a combination of memory data layout and DMA can reduce the DMA preset load by about 86 percent.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.4
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• pp.397-402
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• 2013

In this study, we carried out the each lines of section, using GC (green silicon carbide) whetstone, the SCM415 material which separated by after and before heat treatments process, in 3+2 axis machining centers for integrated grinding after cutting end mill works, the spindle speed 8000 rpm and feed rate 150 mm/min. For the analysis of the centerline average roughness (Ra), we measured by 10 steps stages. Using Finite element analysis, we found the result of the load analysis effect of the assembly parts, when applied the 11 kg's load on both side of the ATC (Automatic tool change) arm. The result is as follows. For the centerline average roughness (Ra) in the non-heat treatment work pieces, are appeared the most favorable in the tenth section are $0.510{\mu}m$, that were shown in the near the straight line section which is the smallest deformation of curve. In addition, the bad surface roughness appears on the path is to long by changing angle, the more inclined depth of cut, because the chip discharging is not smoothly.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.38-49
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• 2001

This paper presents a new voltage down converter(VDC) using charge and discharge current adjustment circuitry that provides high frequency application. This VDC consist of a common driving circuit and compensation circuits: 2 sensors and each driving transistors for controlling gate current of driving transistor. These sensors are operated as adaptive biasing method with high speed and low power consumption. This circuit is designed with a $0.62{\mu}m$ N well CMOS technology. In H-spice simulation results, internal voltage is bounded ( IV, +0.6V) in proposed circuitry when load current rapidly increases and decreases during Gns between 0 and $200m{\Lambda}$. And the recovery time of internal voltage is about 7ns and 10ns when load current increases and decreases respectively. That is fast better than common driving circuit. Total power consumption is about 1.2mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.4
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• pp.309-317
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• 2000

This paper presents the switching angle and voltage to maximize torque/efficiency and minimize torque ripple in the 4-phase 6-poles Switched Reluctance Motor(SRM). SRM drive has high saturation and nonlinear characteristics of inductance. So we cannot hard to find optimal condition by using analytic method. Therefore it is hard to find the operating the switching angle and voltage through the approximated analysis and computer simulation by using SIMULINK according to the speed and torque required by load. From the results, we can say that the optimum average voltage is determined by the load only and the speed is determined by the optimum turn-on/off angle only. And the maximum efficiency and minimum torque ripple depend on switching angle, not on voltage. And then one-chip microcontroller controls the switching angle and voltage of an asymmetrical inverter in the SRM driver. This drive method, which is expect that the driving methods, which are maximizing torque/efficiency and minimizing torque ripple, will be suitable for the electric vehicle, the industrial application and household appliances.