• Title/Summary/Keyword: Chip integration

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Stereo matching algorithm based on systolic array architecture using edges and pixel data (에지 및 픽셀 데이터를 이용한 어레이구조의 스테레오 매칭 알고리즘)

  • Jung, Woo-Young;Park, Sung-Chan;Jung, Hong
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.777-780
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    • 2003
  • We have tried to create a vision system like human eye for a long time. We have obtained some distinguished results through many studies. Stereo vision is the most similar to human eye among those. This is the process of recreating 3-D spatial information from a pair of 2-D images. In this paper, we have designed a stereo matching algorithm based on systolic array architecture using edges and pixel data. This is more advanced vision system that improves some problems of previous stereo vision systems. This decreases noise and improves matching rate using edges and pixel data and also improves processing speed using high integration one chip FPGA and compact modules. We can apply this to robot vision and automatic control vehicles and artificial satellites.

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77-GHz mmWave antenna array on liquid crystal polymer for automotive radar and RF front-end module

  • Kim, Sangkil;Rida, Amin;Lakafosis, Vasileios;Nikolaou, Symeon;Tentzeris, Manos M.
    • ETRI Journal
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    • v.41 no.2
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    • pp.262-269
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    • 2019
  • This paper introduces a low-cost, high-performance mmWave antenna array module at 77 GHz. Conventional waveguide transitions have been replaced by 3D CPW-microstrip transitions which are much simpler to realize. They are compatible with low-cost substrate fabrication processes, allowing easy integration of ICs in 3D multi-chip modules. An antenna array is designed and implemented using multilayer coupled-fed patch antenna technology. The proposed $16{\times}16$ array antenna has a fractional bandwidth of 8.4% (6.5 GHz) and a 23.6-dBi realized gain at 77 GHz.

Engineered human cardiac tissues for modeling heart diseases

  • Sungjin Min;Seung-Woo Cho
    • BMB Reports
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    • v.56 no.1
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    • pp.32-42
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    • 2023
  • Heart disease is one of the major life-threatening diseases with high mortality and incidence worldwide. Several model systems, such as primary cells and animals, have been used to understand heart diseases and establish appropriate treatments. However, they have limitations in accuracy and reproducibility in recapitulating disease pathophysiology and evaluating drug responses. In recent years, three-dimensional (3D) cardiac tissue models produced using tissue engineering technology and human cells have outperformed conventional models. In particular, the integration of cell reprogramming techniques with bioengineering platforms (e.g., microfluidics, scaffolds, bioprinting, and biophysical stimuli) has facilitated the development of heart-on-a-chip, cardiac spheroid/organoid, and engineered heart tissue (EHT) to recapitulate the structural and functional features of the native human heart. These cardiac models have improved heart disease modeling and toxicological evaluation. In this review, we summarize the cell types for the fabrication of cardiac tissue models, introduce diverse 3D human cardiac tissue models, and discuss the strategies to enhance their complexity and maturity. Finally, recent studies in the modeling of various heart diseases are reviewed.

Self-Driving and Safety Security Response : Convergence Strategies in the Semiconductor and Electronic Vehicle Industries

  • Dae-Sung Seo
    • International journal of advanced smart convergence
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    • v.13 no.2
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    • pp.25-34
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    • 2024
  • The paper investigates how the semiconductor and electric vehicle industries are addressing safety and security concerns in the era of autonomous driving, emphasizing the prioritization of safety over security for market competitiveness. Collaboration between these sectors is deemed essential for maintaining competitiveness and value. The research suggests solutions such as advanced autonomous driving technologies and enhanced battery safety measures, with the integration of AI chips playing a pivotal role. However, challenges persist, including the limitations of big data and potential errors in semiconductor-related issues. Legacy automotive manufacturers are transitioning towards software-driven cars, leveraging artificial intelligence to mitigate risks associated with safety and security. Conflicting safety expectations and security concerns can lead to accidents, underscoring the continuous need for safety improvements. We analyzed the expansion of electric vehicles as a means to enhance safety within a framework of converging security concerns, with AI chips being instrumental in this process. Ultimately, the paper advocates for informed safety and security decisions to drive technological advancements in electric vehicles, ensuring significant strides in safety innovation.

The Moisture Absorption Properties of Liquid Type Epoxy Molding Compound for Chip Scale Package According to the Change of Fillers (충전재 변화에 따른 Chip Scale Package(CSP)용 액상 에폭시 수지 성형물 (Epoxy Molding Compound)의 흡습특성)

  • Kim, Whan-Gun
    • Journal of the Korean Chemical Society
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    • v.54 no.5
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    • pp.594-602
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    • 2010
  • Since the requirement of the high density integration and thin package technique of semiconductor have been increasing, the main package type of semiconductor will be a chip scale package (CSP). The changes of diffusion coefficient and moisture content ratio of epoxy resin systems according to the change of liquid type epoxy resin and fillers for CSP applications were investigated. The epoxy resins used in this study are RE-304S, RE310S, and HP-4032D, and Kayahard MCD as hardener and 2-methylimidazole as catalyst were used in these epoxy resin systems. The micro-sized and nano-sized spherical type fused silica as filler were used in order to study the moisture absorption properties of these epoxy molding compound (EMC) according to the change of filler size. The temperature of glass transition (Tg) of these EMC was measured using Dynamic Scanning Calorimeter (DSC), and the moisture absorption properties of these EMC according to the change of time were observed at $85^{\circ}C$ and 85% relative humidity condition using a thermo-hygrostat. The diffusion coefficients in these EMC were calculated in terms of modified Crank equation based on Ficks' law. An increase of diffusion coefficient and maximum moisture absorption ratio with Tg in these systems without filler can be observed, which are attributed to the increase of free volume with Tg. In the EMC with filler, the changes of Tg and maximum moisture absorption ratio with the filler content can be hardly observed, however, the diffusion coefficients of these systems with filler content show the outstanding changes according to the filler size. The diffusion via free volume is dominant in the EMC with micro-sized filler; however, the diffusion with the interaction of absorption according the increase of the filler surface area is dominant in the EMC with nano-sized filler.

Performance Analysis of Signal Acquisition in L2C Assisted GPS Receivers (L2C AGPS 수신기의 신호 획득 성능 분석)

  • Song, Seung-Hun;Park, Ji-Won;Park, Ji-Hee;Sung, Tae-Kyung
    • Journal of Institute of Control, Robotics and Systems
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    • v.17 no.1
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    • pp.61-67
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    • 2011
  • The GPS new civil signal is modulated on the L2 carrier at a frequency of 1227.6MHz. The L2C signal is composed of two multiplexed code signals, which include CM code with a 10,230 chip sequency repeating every 20ms, and CL code which has a 767,250 chip sequency repeating every 1.5 seconds. Thus, the new civil signal have much improved cross correlation properties so that the position fixing can be possible even with very weak signals. However, it requires very long acquisition time because of its long code length. This paper presents an efficient signal acquisition method for L2C AGPS receiver. Snapshot mode and coarse time assistance are assumed and total integration time is given by 1.5 sec. By SNR worksheet and computer simulation, it is proven that L2C signal can be acquired with very weak power less than -150dBm. Considering the acquisition time and the sensitivity, it is recommended that the highest power signal is acquired with CM code first to reduce TTFF. By the timing synchronization, at this time, search space of the code phase for other signals can be greatly reduced so that CL code can be used in signal acquisition to maximize sensitivity with small computation.

Internal Defect Position Analysis of a Multi-Layer Chip Using Lock-in Infrared Microscopy (위상잠금 적외선 현미경 관찰법을 이용한 다층구조 칩의 내부결함 위치 분석)

  • Kim, Seon-Jin;Lee, Kye-Sung;Hur, Hwan;Lee, Haksun;Bae, Hyun-Cheol;Choi, Kwang-Seong;Kim, Ghiseok;Kim, Geon-Hee
    • Journal of the Korean Society for Nondestructive Testing
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    • v.35 no.3
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    • pp.200-205
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    • 2015
  • An ultra-precise infrared microscope consisting of a high-resolution infrared objective lens and infrared sensors is utilized successfully to obtain location information on the plane and depth of local heat sources causing defects in a semiconductor device. In this study, multi-layer semiconductor chips are analyzed for the positional information of heat sources by using a lock-in infrared microscope. Optimal conditions such as focal position, integration time, current and lock-in frequency for measuring the accurate depth of the heat sources are studied by lock-in thermography. The location indicated by the results of the depth estimate, according to the change in distance between the infrared objective lens and the specimen is analyzed under these optimal conditions.

DSSS MODEM Design and Implementation for a Medium Speed Wireless Link (대중저속 무선 통신을 위한 DSSS 모뎀 설계 및 구현)

  • Won Hee-Seok;Kim Young-Sik
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.1 s.343
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    • pp.121-126
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    • 2006
  • This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

뉴로모픽 시스템용 시냅스 트랜지스터의 최근 연구 동향

  • Nam, Jae-Hyeon;Jang, Hye-Yeon;Kim, Tae-Hyeon;Jo, Byeong-Jin
    • Ceramist
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    • v.21 no.2
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    • pp.4-18
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    • 2018
  • Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

Design of a GaN HEMT 4 W Miniaturized Power Amplifier Module for WiMAX Band (WiMAX 대역 GaN HEMT 4 W 소형 전력증폭기 모듈 설계)

  • Jeong, Hae-Chang;Oh, Hyun-Seok;Heo, Yun-Seong;Yeom, Kyung-Whan;Kim, Kyoung-Min
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.2
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    • pp.162-172
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    • 2011
  • In this paper, a design and fabrication of 4 W power amplifier for the WiMAX frequency band(2.3~2.7 GHz) are presented. The adopted active device is a commercially available GaN HEMT chip of Triquint Company, which is recently released. The optimum input and output impedances are extracted for power amplifier design using a specially self-designed tuning jig. Using the adopted impedances value, class-F power amplifier was designed based on EM simulation. For integration and matching in the small package module, spiral inductors and interdigital capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 50 % and harmonic suppression above 40 dBc for second(2nd) and third(3rd) harmonic at the output power of 36 dBm.