• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.365-365
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• 2010

Similar to the superhydrophobic surfaces of lotus leaf, water strider leg is attributed to hierarchical structure of micro pillar and nano-hair coated with low surface energy materials, by which water strider can run and even jump on the water surface. In order to mimick its leg, many effort, especially, on the fabrication of nanohairs has been made using several methods such as a capillarity-driven molding and lithography using poly(urethane acrylate)(PUA). However most of those effort was not so effective to create the similar structure due to its difficulty in the fabrication of nanoscale hairy structures with hydrophobic surface. In this study, we have selected a low surface energy polymeric material of polytetrafluoroethylene (PTFE, or Teflon) assisted with surface modification of CF4 plasma treatment followed by hydrophobic surface coating with pre-cursor of hexamethyldisiloxane (HMDSO) using a plasma enhanced chemical vapor deposition (PE-CVD). It was found that the plasma energy and duration of CF4 treatment on PTFE polymer could control the aspect ratio of nano-hairy structure, which varying with high aspect ratio of more than 20 to 1, or height of over 1000nm but width of 50nm in average. The water contact angle on pristine PTFE surface was measured as approximately $115^{\circ}$. With nanostructures by CF4 plasma treatment and hydrophobic coating of HMDSO film, we made a superhydrophobic nano-hair structure with the wetting angle of over $160^{\circ}C$. This novel fabrication method of nanohairy structures has been applied not only on 2-D flat substrate but also on 3-D substrates like wire and cylinder, which is similarly mimicked the water strider's leg.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Korean Journal of Optics and Photonics
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• v.3 no.4
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• pp.258-265
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• 1992

A low loss optical waveguide of $P_{2}O_{5}-SiO_{2}$on Si substrate is produced by using the chemical vapour deposition method of $SiO_2$ thin films used in Si technology. Propagation loss of the waveguide layer was 1.65 dB/cm as produced and reduced down to 0.1 dB/cm after heat treatment at $1100^{\circ}C$. By using laser lithography and reactive ion etching method $P_{2}O_{5}-SiO_{2}$ waveguide was produced and subsequently annealed at $1100^{\circ}C$.As a result of this annealing the shape of the waveguide core was changed from rectangular to semi-circular form, and the propagation loss was reduced as down to 0.03 dB/cm at 0.6328$\mu$m and 0.04dB/cm at 1.53$\mu$m. We think that the mechanism of the reduction in propagation loss during the heat treatment is the following: 1) The hydrogen bonding in waveguide layer, which causes absorption loss, is dissociated and diffused out. 2) The roughness of the interface and the micro-structure of the waveguide layer is removed. 3) The irregularities in the cross-sectional shape of the waveguide which was induced during the lithographic process were disappeared by flowing of the waveguide core.

• Clean Technology
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• v.24 no.3
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• pp.175-182
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• 2018

In this research, we investigated the cleanliness by optimizing the water content of the aqueous stripper in fluidic strip process. The stripping properties of the photoresist with optimized aqueous stripper were compared with the commercial organic stripper. The stripping performance was evaluated by electrical and optical characteristics on the surface of the transparent electrode that compare with stripped the transparent electrode surface and the rare surface before patterning by the photoresist. As a result of the photoresist stripping process of the organic stripper and the aqueous stripper optimized for water content, the aqueous stripper exhibited better electrical and optical characteristics than the organic stripper. In the case of the fluidic strip process with organic stripper, the photoresist dissolves in the stripper solution during stripping which can cause re-adsorption by contamination. Whereas that the aqueous stripper under development seems to decrease the photoresist dissolution in the stripper solution. Because the cyclodextrin contained in the stripper captures organic photoresist into hall of cyclodextrin which stripped through swelling and tearing. The photoresist residue captured by the cyclodextrin can be filtered. After the fluidic stripping process by different chemical stripping mechanism, the cleanliness of the organic stripper and aqueous stripper was compared and analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.