• 방송공학회논문지
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• 제25권1호
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• pp.36-47
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• 2020

향상된 신뢰-전파 기반 알고리즘인 정규화 최소-합 알고리즘 혹은 오프셋 최소-합 알고리즘은 낮은 연산복잡도와 높은 복호 성능을 보여 LDPC(Low-Density Parity-Check) 부호의 복호에 널리 이용되고 있다. 그러나, 이 알고리즘들은 적절한 정규화 계수와 오프셋 계수가 이용되어야만 높은 복호 성능을 갖는다. 최근 제안된 CMD(Check Node Message Distribution) 차트와 최소자승법을 이용하여 정규화 계수를 찾는 방법은 기존의 계수 도출 방법보다 계산량이 적을 뿐 아니라 각 반복 복호마다 최적의 정규화 계수를 도출할 수 있기 때문에 복호 성능을 높일 수 있다. 본 논문에서는 이 방법을 응용하여 정규화와 오프셋이 조합된 최소-합 알고리즘의 보정 계수 조합의 도출을 위한 알고리즘을 제안하고자 한다. 차세대 방송 통신 표준인 ATSC 3.0용 LDPC 부호의 컴퓨터 모의실험은 제안한 알고리즘을 통해 도출된 보정 계수 조합을 사용하였을 때 타 복호 알고리즘보다 월등히 높은 복호 성능을 가지는 것을 보인다.

• ETRI Journal
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• 제36권4호
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• pp.591-598
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• 2014

This paper proposes a new min-sum algorithm for low-density parity-check decoding. In this paper, we first define the negative and positive effects of the received signal-to-noise ratio (SNR) in the min-sum decoding algorithm. To improve the performance of error correction by considering the negative and positive effects of the received SNR, the proposed algorithm applies adaptive scaling factors not only to extrinsic information but also to a received log-likelihood ratio. We also propose a combined variable and check node architecture to realize the proposed algorithm with low complexity. The simulation results show that the proposed algorithm achieves up to 0.4 dB coding gain with low complexity compared to existing min-sum-based algorithms.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권2호
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권4호
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.

• 한국통신학회논문지
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• 제36권4A호
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• pp.414-422
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• 2011

모바일 WiMAX 표준 IEEE 802.16e의 블록길이 2,304 비트, 부호율 1/2을 지원하는 LDPC(low-density parity-check) 복호기를 설계하였다. 설계된 LDPC 복호기는 최소-합(min-sum) 알고리듬과 layered 복호를 기반으로 $96{\times}96$ 크기의 부행렬을 병렬로 처리하는 부분병렬 구조를 갖는다. 최소-합 알고리듬의 특징을 이용하여 메모리 용량을 감소시킬 수 있는 새로운 방법을 고안하여 적용함으로써 검사노드 메모리 용량을 기존의 방법보다 46% 감소시켰다. Verilog HDL로 설계된 LDPC 복호기를 $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 174,181개의 게이트와 52,992 비프의 메모리로 구현되었으며, Eb/No=2.1dB의 AWGN 채널에 대해 평균 비트 오율 (BER)는 $4.34{\times}10^{-5}$이고, 100 MHz@1.8-V로 동작하여 약 417 Mbps의 성능을 갖는다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.771-774
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• 2010

본 논문에서는 WiMAX용 LDPC(Low-Density Parity Check) 복호기의 비트오율 성능 분석을 통해 최적 설계 사양을 도출하였다. LLR SPA(LLR Sum-Product Algorithm)을 근사화 시킨 최소합 알고리듬(Min-Sum Algorithm; MSA)을 Matlab으로 모델링한 후, 시뮬레이션을 통해 LLR 비트 폭과 최대 반복 복호 횟수에 따른 비트오율(Bit Error Rate; BER) 성능을 분석하였다. 모델링된 LDPC 복호기는 IEEE 802.16e 표준에 제안된 블록길이 2304, 부호화율 1/2인 PCM(Parity Check Matrix)을 사용하였으며, QPSK 변조와 백색 가우시안 잡음채널 하에서 시뮬레이션 하였다. 비트오율 성능을 분석한 결과, LLR 비트 폭은 (8,6)이고 반복 복호 횟수는 7인 경우에 비트오율 성능이 가장 우수함을 확인하였다.

• ETRI Journal
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• 제34권4호
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• pp.629-632
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• 2012

This letter investigates the combination of the Chase-2 and sum-product (SP) algorithms for low-density parity-check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low-weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.

• ETRI Journal
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• 제37권1호
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• 반도체디스플레이기술학회지
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• 제21권1호
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.