• 한국자동차공학회논문집
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• 제17권4호
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• pp.93-100
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• 2009

Intake/exhaust valve timing and exhaust cam lift were changed to control the internal exhaust gas recirculation (IEGR) and combustion phase of homogeneous charge compression ignition (HCCI) engine. To measure the IEGR rate, in-cylinder gas was sampled during from intake valve close to before ignition start. The lower exhaust cam made shorter valve event than higher exhaust cam and made IEGR increase because of trapping the exhaust gas. IEGR rate was more affected by exhaust valve timing than intake valve timing and increased as exhaust valve timing advanced. In-cylinder pressure was increased near top dead center due to early close of exhaust valve. Ignition timing was more affected by intake valve timing than exhaust valve timing in case of exhaust valve lift 8.4 mm, while ignition timing was affected by both intake and exhaust valve timing in case of exhaust valve 2.5 mm. Burn duration with exhaust valve lift 2.5 mm was longer than other case due to higher IEGR rate. The fuel conversion efficiency with higher exhaust valve lift was higher than that with lower exhaust valve lift. The late exhaust and intake maximum open point (MOP) made the fuel conversion efficiency improve.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.9-12
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• 1998

Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• 한국통신학회논문지
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• 제16권11호
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• pp.1179-1185
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• 1991

초박막 재산화 질화산화막을 $1050^{\circ}C-1100^{\circ}C$ 온도에서 20, 40초 동안 산소 분위기에서 램프 가열 방법의 급속 열처리 공정에 의해 형성 시켰다. 초박막의 전기적 특성은 누설전류, 항복전압, 시간종속 항복과 F-N 관통을 분석 하였다. 질화와 재산화 조건에 따른 전하포획의 의존성 즉 고전계 스트레스에 유기되는 항복전하량$(Q_{BD})$ 증가 여부와 평탄대역 전압이동$(\DeltaV_{FB})$을 연구하였다. 분석 결과에 의하면, 급속 열처리 재산화시 유전적 성질이 상당히 개선되었고, 항복전하량은 증가되었으며, 평탄대역전압은 감소 되었다.

• 오토저널
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• 제15권1호
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• pp.55-66
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• 1993

The characteristics of the flow processes in the cylinder of the two-stroke cycle engines have become the subject of increasing and attention owing to the simplicity and the higher power per unit weight of the two-stroke cycle engine. Among the many factors which influence on the scavenging flow, the port angle is important factor. Hence, four different type models with one inlet-port and two side-ports are studied to show the effect of port angle on the laminar scavenging flow. When the inlet-port axial is relatively larger than the side-port axial angle, it is showed that the fresh charge penetrate into the burned gas and displace it first toward the cylinder head and then toward the exhaust port. When the inlet-port axial angle is much less than the side-port axial angle, the fresh charge through the inlet-port directly move toward the exhaust port. The result showed that the model A may suppress the generation of vortices in the vicinity of inlet and side prots which restrict the sufficient supply of fresh charge and obstruct the perfect displacement of all combustion products.

• 한국전자통신학회논문지
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• 제11권5호
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• pp.473-478
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• 2016

본 논문은 RTP법으로 산화막을 질화시킨 질화산화막으로 MIS 커패시터를 제작하여 avalanche 주입에 따른 캐리어 트랩 특성을 조사하였다. avalanche 주입에 의한 flatband 전압 변화는 두 번의 turn-around가 관찰되었는데 이는 처음 산화막에서 전자 트래핑이 있어나고, 전하 주입에 따라 홀 트래핑에 의한 turn-around 후 다시 전자 트래핑이 일어나는 것을 관찰하였다. 질화 산화막의 캐리어 트랩 파라미터를 결정하기 위하여 실험 결과를 기초로 종류가 다른 여러 트랩을 갖는 계에 대한 캐리어 트래핑을 비교한 결과 실험값과 일치함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• 한국전기전자재료학회논문지
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• 제24권3호
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• pp.182-187
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• 2011

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift (${\Delta}V_{\mathrm{T}}$) of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2~3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.