• 한국재료학회지
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• 제14권7호
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• pp.516-521
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• 2004

We applied a deuterium plasma treatment to the surface of polycrystalline silicon films using PECVD and observed the change with AFM, XRD, ET-IR, and SIMS measurement. A bias temperature stressing (BTS) test was carried out to evaluate the reliability of the thin-film transistors (TFT). TFTs with channel lengths as small as 2 ${\mu}m$ were electrically stressed fer up to 1000 sec at room temperature. From the parameter variation such as s-factor, leakage current and on/off ratio, we suggest that the deuterium plasma treatment suppress the hot carrier effect and improve the stability of TFTs.

• Transactions on Electrical and Electronic Materials
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• 제16권2호
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• pp.78-81
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• 2015

Pure ZnO and ZnO nanowires doped with 3 wt.% Ga (‘3GZO’) were grown by pulsed laser deposition in a furnace system. The doping of Ga in ZnO nanowires was analyzed by observing the optical and chemical properties of the doped nanowires. The diameter and length of nanowires were under 200 nm and several ${\mu}m$, respectively. Changes of significant resistance were observed and the sensitivities of ZnO and 3GZO nanowires were compared. The sensitivities of ZnO and 3GZO nanowire sensors measured at 300℃ for 1 ppm of ethanol gas were 97% and 48%, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.

• Journal of Information Display
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• 제8권4호
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• pp.15-18
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• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.16-19
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• 2007

In this paper, we present work that has been carried out using the SLS process to control grain boundary(GB) location in TFT channel region and it is possible to locate the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analyzed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.457-460
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• 1999

The effects of electrical positive stress on n-channel LDD and offset structured poly-Si TFT\`s have been systematically investigated in order to analyze the transfer curve\`s shift mechanism. It has been found that the LDD and offset regions behave as a series resistance that reduce the electric field near drain. Hot carrier effects are reduced because of these results. After electrical stress transfer curve’s shift and variation of the off-current are dependent upon the offset length rather than offset region’s doping concentration. Variation of the subthreshold slope is dependent upon offset region’s doping concentration as well as offset length.

• 한국진공학회지
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• 제2권2호
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• pp.188-198
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• 1993

두께가 6~10 nm인 게이트 산화막의 계면에 염소(Cl)를 도입시킨 n-MOS capacitor 및 n-MOSFET을 제잘하여 물성적인 방법(SIMS, ESCA)과 전기적인 방법에 의해서 소자의 특성을 분석, 평가하였다. Last step TCA법을 이용하여 성장시킨 산화막은 No TCA법으로 성장시킨 것보다 mobility가 7% 정도 증가하였고, 결함 밀도도 감소하였다. Time-zero-dielectric-breakdown(TZDB)으로 측정한 결과, Cl를 도입한 막의 파괴 전계(breakdon field)는 18 MV/cm인데, 이것은 Cl을 도입하지 않은 것보다 약 0.6 MV/cm 정도 높은 값이다. 또한 time-dependent-dielectric-breakdown(TDDB) 결과로부터 수명이 20년 이상인 것으로 평가되었고, hot carrier 신뢰성 측정으로부터 평가한 소자의 수명도 양호한 것으로 나타났다. 이상의 결과에서 Cl을 계면에 도입시킨 게이트 산화막을 가진 소자가 좋은 특성을 나타내고 있으므로 Last step TCA법을 종래의 산화막 성장 방법 대신에 사용하면 MOSFET 소자의 새로운 게이트 절연막 성장법으로서 대단히 유용할 것으로 생각된다.

• 한국전기전자재료학회논문지
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• 제24권6호
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.