• Smart Structures and Systems
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• v.29 no.5
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• pp.661-675
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• 2022

In this paper, an electric vehicle drives with efficient control and low cost hardware using four quadrant DC converter with Permanent Magnet Direct Current (PMDC) motor fed by DC boost converter is presented. The main idea of this work is to improve the energy efficiency of the conversion chain of an electric vehicle by inserting a boost converter between the battery and the four quadrant-DC motor chopper assembly. Consequently, this method makes it possible to maintain the amplification gain of the 4 quadrant chopper constant regardless of the battery voltage drop and even in the presence of a fault in the battery. One of the most important control problems is control under heavy uncertainty conditions. The higher order sliding mode control technique is introduced for the adjustment of DC bus voltage and mechanical motor speed. To implement the proposed approach in the automotive field, experimental tests were carried out. The performances obtained show the usefulness of this system for a better energy management of an electric vehicle and an ideal control under different operating conditions and constraints, mostly at nominal operation, in the presence of a load torque, when reversing the direction of rotation of the motor speed and even in case of battery chamber failure. The whole system has been tested experimentally and its performance has been analyzed.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.2
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• pp.80-86
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• 2003

In this paper, a new three-phase voltage-source inverter topology for high voltage and high Power applications is proposed to improve the quality of output voltage waveform. A chain converter which is used as an auxiliary circuit generates a ripple voltage and injects it to the conventional 12-step inverter. Thus, the injection of the ripple voltage results in 36-step operation with a link and 60-step operation with two links. The proposed inverter is compared to the conventional multilevel inverter in the viewpoint of ratings of phase- shifting transformers, switching devices and capacitors employed. The proposed scheme is simple to control capacitor voltages compared to the conventional schems and is cost effective for high voltage and high power application over several tens of MVA. The proposed approach is validated through simulation, and the experimental results are provided from a 2KVA laboratory prototype.

• Journal of Biomedical Engineering Research
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• v.12 no.4
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• pp.255-260
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• 1991

A system using a personal computer has been developed for Polymerase Chain Reaction, an amplifying process of specific DNA. This system is composed of software and hardware which contains a control system, a heating and cooling system, a multichannel A/D converter, and a personal computor. The software is programmed'in assembly'and basic language. The newly developed PCR system which is controlled by the program of the personnal computor can be applied 1.o the amplification of various DNA. This system was tested by using Mycobacterium tuberculosis DNA and showed the DNA band on the UV transilluminator.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.942-946
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• 2009

A scan order converter has to be placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. Recently a hardware architecture has been proposed to implement a scan converter based on the single line memory. Since both read and write accesses happen at each cycle, however, the largest part of the entire power budget is occupied by the SRAM itself. In this paper, the data packing and unpacking procedure is inserted in the processing chain, such that the access frequency to the SRAM is reduced to 1/8 by adopting a packed larger data unit. The simulation results show that the resultant power consumption is reduced down to 16% for the SXGA resolution.

• ETRI Journal
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• v.30 no.4
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.7
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• pp.916-923
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• 2014

This paper proposes a low-cost switched-mode rectifier (SMR) for a small-scale wind turbine with a permanent magnet synchronous generator (PMSG) system. Also, a sensorless Fuzzy MPPT control is realized by the proposed system. In the PMSG system with the SMR, the synchronous impedance can be replaced as the input inductor of a boost converter. Moreover, the sensorless MPPT control using the Fuzzy technique is carried out by the duty-ratio regulation of the SMR. The relation between the generating power and the duty-ratio is ruled by the chain rule. The wind turbine model is implemented by the squirrel cage induction motor and generated the variable torque when the generator speed is varied. To verify the performance of the proposed system, simulation and experimental results are executed.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.5
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• pp.450-456
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• 2005

In this paper new 60-step inverter system for medium-to-large scale STATCOM is proposed and operating principle along with control method is detailed. A simple auxiliary circuit is employed to Improve output voltage waveform of 12-step into 60-step. The proposed scheme could be a cost effective approach in high power application such as 10Mvar to 30Mvar STATCOM. Experimental results from a 2KVA laboratory prototype show validity of the proposed method.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.36-41
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• 2004

In this paper a large scale STATCOM using double-connected multi-step inverter is proposed and operating principle along with control method is detailed. A simple auxiliary circuit including an interphase transformer is employed to improve output voltage waveform of 12-step into 36-step. The proposed scheme could be a cost effective approach in high power applications such as 10MVar to 30MVar STATCOM. Experimental results from a 2KVA laboratory prototype show validity of the proposed method.