• Child Studies in Asia-Pacific Contexts
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• v.7 no.1
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• pp.1-13
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• 2017

The rich cultural backgrounds and practices of children from native cultures are often absent in classroom instruction, as teachers might feel that they have inadequate knowledge and backgrounds in the unique practices of these populations. Historically, children from native cultures have had challenging educational experiences and poor educational outcomes. To address these challenges, we propose a Family and Culture Based (FCB) framework that draws from family-centered practice, asset-based practice, and culturally responsive pedagogy. This article describes the three steps of the FCB framework, which uses a teacher-as-learner approach to instruct students from native cultures by engaging teachers in reflection, gaining knowledge about the cultural practices of the family and community, and integrating the new knowledge into practice. We use a Pacific Islands case (Native Hawaiian family) and a Pacific Northwest case (First Nations family) to illustrate the potential benefits of using the FCB framework with indigenous students.

• Journal of Educational Research in Mathematics
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• v.26 no.3
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• pp.421-442
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• 2016

This study analyzed characteristics which emerged while 38 secondary school teachers observed a video clip about a centroid of triangles instruction. The aim of this study based on the analysis was to deduce implications in terms of the various means which would enhance teachers' knowledge in teaching mathematics and assist in designing mathematics education programs for teachers and professional development initiatives. To achieve this goal, this research firstly reviewed previous studies relevant to the 'Knowledge Quartet' as a framework of analyzing teachers' knowledge in mathematics instructions. Secondly, this study probed the observation results from the teachers in the light of the KQ. Therefore, some issues in the teacher education program for teaching mathematics were thirdly identified in the categories of 'Foundation', 'Transformation', 'Connection', and 'Contingency' based on the analysis. This research inspires the elaboration of what features have with regard to effective teachers' knowledge in teaching mathematics through the analyzing process and additionally the elucidation of essential matters related to mathematics education on the basis of the analyzed results.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.396-399
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• 1999

In this paper, the efficient HW/SW co-simulation method which selects the ISA model dynamically is proposed. Because the ISA models with only fixed accuracy have been used in previous co-simulation environment, it may result in bad performance in speed or accuracy. In the proposed method, the cycle accurate ISA model is used in the case that the states of the detailed system are to be inspected. In other case, instruction-based model is executed in order to accelerate the simulation speed. The proposed dynamic model selection can be done by setting the conversion point in the application code before the simulation starts. The experiment on the embedded RISC processor have been performed, and its result shows that the proposed method is more efficient than the case of using fixed ISA model.

• Journal of Korean Society for Quality Management
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• v.49 no.3
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• pp.269-279
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• 2021

Purpose: The purpose of this study was to suggest weapon system specifications for requirements of Condition-Based Maintenance(CBM/CBM⁺). Methods: The military documents and case studies with regard to condition-based maintenance were reviewed. Representative Korea defense specifications of weapon system such as an aircraft, a C4ISR etc. were analyzed and investigated the level of requirement for maintainability was. Results: Condition-based maintenance was defined in both U.S. instruction and Korean directive. While deparment of defense(U.S.) provide a guidebook for CBM⁺, detailed instruction was not sufficient for Korean. Ministry of national defense(ROK) define the CBM⁺ by means of IPS element which should be developed along with the system development. The maintainability was barely included in Korean defense specifications, except for BIT(Built-in test) function. As a first step for defining the condition-based maintenance requirement in defense specification, this study suggests a standard form for data needed to acquire according to types of system, fault, failure, and so on. Conclusion: The empirical researches on CMB/CBM⁺ with domestic weapon systems are not enough, and a logic which leads the maintenance strategy to CMB/CBM⁺ is not solved. Through technical researches and institutional improvements including this study, we hope that condition-based maintenance would be fully established in the Korean defense field.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.1-7
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• 2005

Web-Based instruction system implemented according to CGI based process-oriented. But, in case of system development, theses method is able to take inefficiency with duplication of program code. Also, ofter the development, it takes difficult on the operation and management. In this research, I implement Web-based score processing system by component composition. Applied component model is Java Beans and composition method is to use Chiron-2 architecture. By this method, this research shows the high efficiency - not only structural advance but also low value of cyclomatic complex that measure a maintenance.

• Journal of Science Education
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• v.41 no.2
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• pp.248-266
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• 2017

The purpose of this study is to present various examples of collaborative learning based on the Instruction of Internet in the 6th grade elementary school mathematics class. So we introduce the design method of classroom environment for classroom Internet and give example of various teaching methods. This study was conducted for nine months from March to November, 2016, one sixth grade of elementary school in D area. During this period, we conducted Instruction of Internet-based collaborative learning to classify typical teaching cases. We classified into 5 type collaborative learning. First, collaborative learning in the classroom. Second, remote collaborative learning between classroom and classroom. Third, Live participation classes. Forth, project collaborative learning. Fifth, using virtual reality in collaborative learning. In addition, we could identify that there is a difference compared to the conventional learning. It became possible to conduct collaborative learning with other students simultaneously or have opening class with both parents and teachers by using Youtube. These examples can be presented as a case to depart from traditional mathematics class in one classroom. In this regard, we will be able to provide several implications about teaching methods utilizing smart device and Internet in future classroom.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.200-208
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• 2000

Multi-ports register could shared several instructions at the same time in read operation. We address a formal methods for describing timing analysis and resource restriction in pipeline super scalar process that having multi-Port registers. First, we specify in-order pipeline instructions, and then, extend timing analysis in out-of-order super-scalar. In this case, we find instruction pairs in any cycle which can execute same time, We use ACSR(Algebra of Communicating Shared Resources), a branch of formal methods based on process algebra, for instruction specification and modelling.

• Proceedings of the Korea Contents Association Conference
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• 2006.05a
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• pp.246-250
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• 2006

As a result of the rapid development in the digital content industry, designers have to visualize colors across a range of digital media in a relevant and sophisticated manner. The purpose of this study is to develop a new digital color design education curriculum for enhancing learners' capability of digital color management. This study presents an original university-level color design curriculum for digital color learning that includes traditional color learning. In order to develop interactive pedagogy that provides diverse color experiences to students, this study suggestes a blended learning method that combines face-to-face instruction and web-based instruction. Through two case studies at universities, this paper illustrate the effectiveness of the proposed digital color design curriculum.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.512-521
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• 2002

Recently, conventional superscalar RISC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(Instructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.