• Journal of Power Electronics
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• 제14권6호
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• pp.1139-1146
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• 2014

Digital signal processor (DSP) and field programmable gate array (FPGA) based concentrated control systems are designed for implementing CPS-SPWM strategies. The self-defined universal asynchronous receiver/transmitter (UART) protocol is used for communication between a master controller and an individual module controller via high speed links. Aimed at undesired pulse competition, this paper analyzes its generation mechanism and presents a new method for eliminating competition pulses with no time delay. Finally, the proposed concentrated controller is applied to a 10kV/10MVar distribution static synchronous compensator (DSTATCOM) industrial prototype. Experimental results show the accuracy and reliability of the concentrated controller, and verify the superiority of the proposed elimination method for competition pulses.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 추계학술대회 논문집
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• pp.121-122
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• 2014

멀티 레벨 인버터는 높은 출력 전압을 갖으며, 낮은 THD(Total harmonic distortion)를 요구하는 시스템에 적합하다. 그 중 cascaded H-brige 멀티레벨 인버터는 H-bridge 셀별 관리가 쉽고, 레벨 수를 증가시키기 쉽다는 장점 때문에 많이 이용되어 왔다. 본 논문에서는 cascaded H-bridge 인버터의 기존 PI (proportional integral) 제어 기반 PWM (pulse width modulation)기법의 스위칭 패턴과 모델 예측 제어의 스위칭 패턴을 비교하고 모델예측 제어 시 셀 별 스위칭 패턴 균형을 위한 방법을 제안한다.

• Journal of Power Electronics
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• 제17권3호
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• pp.664-673
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• 2017

With the development of multilevel converters, cascaded single-phase H-bridge rectifiers (CHBRs) has become widely adopted in high-voltage high-power applications. In this study, sequence pulse modulation (SPM) is proposed for CHBRs. SPM is designed to balance the dc-link voltage and maintain the smooth changes of switch states. In contrast to phase disposition modulation, SPM balances the dc-link voltage even after removing the load of one submodule. The operation principle of SPM is deduced, and the unbalance degree of SPM is analyzed. All the proposed approaches are experimentally verified through a prototype of a four-module (nine-level) CHBR. Conclusions are drawn in accordance with the results of SPM and its imbalance degree analysis.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.79-80
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• 2015

멀티레벨 인버터에 널리 사용되는 Phase Shifted PWM은 셀 간의 동일한 전력 분배가 가능하나 각 셀 carrier의 위상차이로 인해 무부하 운전시 특정 셀에 회생이 발생하고, 지령 전압과 실제 전압의 위상차가 발생하는 단점이 있다. Level Shifted PWM을 통해 이와 같은 단점을 보완할 수 있으나, 각 셀의 스위칭 패턴이 모두 달라 전력 분배가 동일하게 이루어 지지 않는 문제가 있다. 본 논문에서는 기존의 Level Shifted PWM 방법을 개선하여 각 셀의 스위칭 패턴을 순환시켜 셀 간 동일한 전력분배가 이루어지도록 하였고, 시뮬레이션을 통해 이를 검증하였다.

• Journal of Power Electronics
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• 제13권2호
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• pp.296-303
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• 2013

This paper proposes a high efficiency three-phase cascaded phase shifted H-bridge multi-level inverter without DC/DC converters for grid-tied multi string photovoltaic (PV) applications. The cascaded H-bridge topology is suitable for PV applications since each PV module can act as a separate DC source for each cascaded H-bridge module. The proposed phase shifted H-bridge multi-level topology offers advantages such as operation at a lower switching frequency and a lower current ripple when compared to conventional two level topologies. It is also shown that low ripple sinusoidal current waveforms are generated with a unity power factor. The control algorithm permits the independent control of each DC link voltage with a maximum power point for each string of PV modules. The use of the controller area network (CAN) communication protocol for H-bridge multi-level inverters, along with localized PWM generation and PV voltage regulation are implemented. It is also shown that the expansion and modularization capabilities of the H-bridge modules are improved since the individual inverter modules operate more independently. The proposed topology is implemented for a three phase 240kW multi-level PV power conditioning system (PCS) which has 40kW H-bridge modules. The experimental results show that the proposed topology has good performance.

• 전기학회논문지
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• 제67권7호
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• pp.846-853
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• 2018

In this paper, an improved model predictive control (MPC) method is proposed, which reduces the amount of calculations caused by the increased number of candidate voltage vectors with the increased voltage level in multi-level inverters. When the conventional MPC method is used for multi-level inverters, all candidate voltage vectors are considered to predict the next-step current value. However, in the case that the sampling time is short, increased voltage level makes it difficult to consider the all candidate voltage vectors. In this paper, the improved MPC method which can get a fast transient response is proposed with a small amount of the computation by adding new candidate voltage vectors that are set to find the optimal vector. As a result, the proposed method shows faster transient response than the method that considers the adjacent vectors and reduces the computational burden compared to the method that considers the whole voltage vector. the performance of the proposed method is verified through simulations and experiments.

• Journal of Power Electronics
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• 제9권2호
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.

• Journal of Power Electronics
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• 제18권1호
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

• Journal of Power Electronics
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• 제18권4호
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Journal of Power Electronics
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• 제12권5호
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• pp.739-747
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• 2012

This paper applies carrier phase shifted pulse-width modulation (CPS-PWM) to transformerless modular multilevel converters (MMC) to improve the output spectrum. Because the MMC topology is characterized by the double-star connection of six legs consisting of cascaded modular chopper cells with floating capacitors, the balance control of the DC-link capacitor voltage is essential for safe operation. This paper presents a leg-balancing control strategy to achieve DC-link voltage balance under all operating conditions. This strategy based on circulating current decoupling control focused on DC-link balancing between the upper and lower legs in each phase pair by considering the six legs as three independent phase-pairs. Experiments are implemented on a 100-V 3-kVA downscaled prototype. The experimental results show that the proposed leg-balancing control is both effective and practical.