• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.34-42
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• 1993

An analytic approach to wide-band amplification using simplified equivalent MESFET modeling has enabled an ultrabroad-band flat-gain amplifier from DC to microwave. The developed lossy-match ultrabroad-band amplifier operates as a RC coupled circuit in the low-frequency range and lossless impedance matching circuit in the microwave frequency range with gain compensation circuits. The reduced gain caused by external resistors is compensated using 2-stage cascade amplification, and the gain of designed unit is 12.5.+-.1dB from the vicinity of DC to 7GAz. The experimental gain characteristics are good agreement with computer simulated results. The input and output VSWRs are measured under 2:1 over the operating frequency range, and the gain goes down over 15dBrange with various gate bias voltages.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.259-262
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications. The proposed circuit has been designed by using TSMC $0.18{\mu}m$ CMOS process and current-reused two-stage cascade topology. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results shows that the LNA has a extremely low power dissipation of 1.38mW with a $V_{DD}$ of 1.0V. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and noise figure of 1.13dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.101-106
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• 2014

This paper presents a wide dynamic range radio-frequency (RF) root-mean-square (RMS) power detector using an automatic gain control (AGC) loop. The AGC loop consists of a variable gain amplifier (VGA), RMS conversion block and gain control block. The VGA exploits dB-linear gain characteristic of the cascade VGA. The proposed circuit utilizes full-wave squaring and generates a DC voltage proportional to the RMS of an input RF signal. The proposed RMS power detector operates from 500MHz to 5GHz. The detecting input signal range is from 0 dBm to -70 dBm or more with a conversion gain of -4.53 mV/dBm. The proposed RMS power detector is designed in a 65-nm 1.2-V CMOS process, and dissipates a power of 5 mW. The total active area is $0.0097mm^2$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.861-864
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• 2005

Performing accurate and repeatable low frequency noise measurement is critical for modeling and simulation of flicker noise. Through the accurate and repeatable on-wafer measurement, low frequency noise characteristics of the 0.18 ${\mu}m$ n-MOSFETs are discussed. And on-wafer flicker noise measurement system is presented. The on-wafer measurement system consists of cascade probe station, low noise current amplifier (SR570), and dynamic signal analyzer (HP35670A).

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.1
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• pp.19-26
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• 2011

In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and 1-bit SDM(Sigma- Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type I Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Korean Journal of Optics and Photonics
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• v.19 no.3
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• pp.237-241
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• 2008

An all-optical encryption system built on the basis of electrical logic circuit design principles is proposed, using semiconductor optical amplifier (SOA) exclusive or (XOR) logic gates. Numerical techniques (steady-state and dynamic) were employed in a sequential manner to optimize the system parameters, speeding up the overall design process. The results from both numerical and experimental testbeds show that the encoding/decoding of the optical signal can be achieved at a 10 Gbps data rate with a conventional SOA cascade without serious degradation in the data quality.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.195-200
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• 2018

A W-band frequency octupler is implemented on 100-nm GaAs pHEMT process. The fabricated octupler can be used as a local oscillator or a signal source of W-band transceivers. Three common-source doublers are connected in cascade to multiply an input signal of 10.75 GHz to 83 GHz. A common-source amplifier is followed for each doubler to improve the conversion gain and suppress the unwanted harmonics. The fabricated octupler showes high output of more than 6 dBm in the 80 - 84 GHz band and achieved excellent spurious suppression performance over 20 dBc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.89-94
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• 2008

In this paper, a cascade of a wideband amplifier and a high-Q bandpass filter (BPF) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion receivers. The wideband amplifier is designed to obtain the -3dB bandwidth of 5.4GHz, and the high-Q BPF is designed to select a 2.4GHz RF signal for the Bluetooth specifications. The measured results demonstrate 18.8dB power gain at 2.34GHz with 31MHz bandwidth, corresponding to the quality factor of 75. Also, it shows the noise figure (NF) of 8.6dB, and the broadband input matching (S11) of less than -12dB within the bandwidth. The whole chip dissipates 64.8mW from a single 1.8V supply and occupies the area of $1.0{\times}1.0mm2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.