• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2980-2988
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• 1998

This paper describes the design of asynchronous adders based on carry selection and carry bypass techniques. The designs are faster than existing asynchronous adders which are based on ripple carry technique. It is caused by reducing the carry transfer time by using carry selection and carry bypass techniques. Also, the design uses tree structure to reduce the completion sensing time. The proposed adders are designed with CMOS domino logic and experimented with HSPICE simulator. Experimental results show that the proposed adders can be faster about 50% in average cases than previous ripple carry adders.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1748-1751
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• 2002

An expression for the average carry propagation delay in a ripple carry adder is obtained which is exact up to terms of the order 0(n$\^$-1/ln n). The case of several adders working in parallel is also considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.32-36
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• 2008

Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.339-342
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• 2005

동적 부분 재구성은 FPGA 칩에 구현된 디자인에서 변경이 필요한 부분만 재구성하여 줌으로써 실시간적 재구성을 가능하게하는 방법이다. 동적 부분 재구성에 대한 많은 연구를 통하여 게이트 수준의 부분 재구성이 가능하지만, 설계 복잡도가 큰 시스템을 설계시에 게이트 수준의 부분 재구성 방법은 부적적하다. 본 논문에서는 Xilinx에서 제고하는 버스 매크로를 사용하여 모듈 기반의 부분 재구성 기법에 대하여 기술하며, 곱셈기, 레지스터, 그리고 ripple carry adder로 구성된 회로에서 ripple carry adder를 carry lookahead adder로 재구성한다.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1998.10a
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• pp.222-227
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• 1998

The paper proposes a new method for measuring the flow ripple generated by an axial piston pump and motor in a hydrostatic transmission. The method is based on dynamic characteristics between pressure and flow ripple in the pipeline. Also, the self-checking functions develop for the evaluation of accuracy and dynamic response of estimated results by the method proposed here. The experiment carry out open circuit type hydrostatic transmission. By using the self-checking functions, the validity of the method is investigated by comparison with the measured and estimated flow and pressure ripples, and good agreement is achieved.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.62-65
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• 2011

FPGA는 대용량의 게이트를 지원하는 하드웨어를 프로그램 할 수 있는 디바이스이다. ASIC을 위해 설계된 로직은 칩으로 제조되기 전에 검증 과정을 거친다. 이 검증 과정에서 시뮬레이션의 한계를 극복하기 위해 FPGA를 사용한 에뮬레이션 방법을 많이 채택한다. 에뮬레이션 과정에서 ASIC의 동작 속도로 검증하는 것이 바람직하지만 FPGA의 특성상 ASIC과 같은 속도로 동작하기는 쉽지 않은 것이 현실이다. 본 논문에서는 HDL 코딩 방법에 따른 FPGA의 성능 민감도를 실험하였다. 실험 및 평가를 위해 다양한 알고리즘을 가진 가산기를 이용하였고 각 가산기 종류와 비트수에 따라 Verilog-HDL을 이용하여 코딩하였으며 대표적인 FPGA 제조사(Altera와 Xilinx)별, 디바이스별로 동작 속도와 자원 사용량을 측정하였다. 실험 결과 FPGA 제조사별로 다른 경향을 보임을 확인하였다. 성능 면에서는 비트별로 다소 차이는 있지만 Altera 디바이스에서는 Ripple Carry, Carry Lookahead 가산기보다 Prefix 가산기의 성능이 우수하게 나왔다. Xilinx 디바이스에서는 예상과 달리 가산기들 사이의 성능 차이가 크게 나지 않았으며 Ripple Carry, Carry Lookahead 가산기가 Prefix 가산기보다 높은 성능을 보이는 경우도 있었다. 비용 면에서는 디바이스별로 큰 차이가 나지 않았으며 ASIC과 비슷한 성능 민감도를 보였다. 그리고 각 제조사에서 제공하는 IP(Intellectual Property) Core를 사용했을 경우는 대부분의 디바이스에서 우수한 성능을 보여 주었다. TSMC 90nm 공정 기술로 제작한 ASIC과 IP Core를 비교했을 때는 ASIC의 성능이 4배 정도 우수한 것으로 나타났다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.11
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• pp.491-494
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• 2006

In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.843-846
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• 1998

산술연산을 수행하는 가산기는 ALU(arithmetic logic unit)의 성능을 좌우하는데 매우 중요한 역할을 하며, 어떠한 캐리 생성 방식을 사용하는냐에 따라 그 성능이 결정될 수 있다. RCA(Ripple carry adder)는 간단하고, 쉬운 설게로 널리 사용되자만, 캐리의 전파지연 문제로 인해 고속의 가산기 응용에의 부적합하다. 또한, CLA(carry lookahead adder)방식의 가산기는 캐리의 지연시간이 가산기의 단수와 무관하므로, 연산속도를 높일 수 있는 장점이 있지만 더하고자 하는 bit의 수가 클수록 회로가 매우 복잡해지는 큰 단점을 가지고 있다. 따라서, 본 논문에서는 간단하면서도 성능이 우수한 64bit 가산기를 설계하고 시뮬레이션을 통하여 설계된 회로의 우수성을 증명하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.53-57
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• 2012

In this paper, by designing 20 W class driving circuit for driving high-power LED (Light Emitting Diode), we are going to comparatively carry out the analysis of characteristics for power circuit according to each design method. In this case, 200 V 60 Hz was performed as input data. The electrical characteristics such as voltage, current and ripple are checked for constant current circuit and constant voltage circuit in the LED module. In addition, as the ripple has an influence on illumination of LED light, low temperature working (-20 [$^{\circ}C$]) and high temperature working(80 [$^{\circ}C$]) are measured to make sure the ripple characteristics in accordance with temperature. In low temperature operation -20 [$^{\circ}C$] measurements, both constant current circuit and constant-voltage circuit were less impacted on input fluctuation, whereas in the high temperature operation 80 [$^{\circ}C$], current voltage in constant voltage circuit was surge after 430 [hour]. Voltage current ripple of constant current circuit was much less than constant voltage circuit, therefore we can show that constant current circuit is more stable.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.31 no.4
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• pp.209-220
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• 2019

Even though the scale of hard structures for beach stabilization should carefully be determined such that these structures do not interrupt the great yearly circulation process of beach sediment in which the self-healing ability of natural beach takes places, massive hard structures such as the submerged breakwater of wide-width are frequently deployed as the beach stabilization measures. On this rationale, asymmetric ripple mat by Irie et al. (1994) can be the alternatives for beach stabilization due to its small scale to replace the preferred submerged breaker of wide-width. The effectiveness of asymmetric ripple mat is determined by how effectively the vortices enforced at the contraction part of flow area over the mat traps the sediment moving toward the offshore by the run-down. In order to verify this hypothesis, we carry out the numerical simulations based on the Navier-Stokes equation and the physically-based morphology model. Numerical results show that the asymmetric ripple mat effectively capture the sediment by forced vortex enforced at the apex of asymmetric ripple mat, and bring these trapped sediments back to the beach, which has been regarded to be the driving mechanism of beach stabilization effect of asymmetric ripple mat.