• 한국전기전자재료학회논문지
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• 제27권2호
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.98-103
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• 2008

1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

• 전기전자학회논문지
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• 제28권3호
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• pp.369-374
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• 2024

본 논문에서는 차세대 메모리 기술로 주목받고 있는 커패시터리스 디램(one-transistor DRAM, 1T-DRAM)을 소자의 설계 최적화에 대해 다룬다. 기존 커패시터기반 DRAM의 한계를 해결하고자, 비대칭 듀얼 게이트 구조를 사용하여 보유 시간 및 성능을 향상시키는 방향성을 제시한다. ZTC(Zero-temperature coefficient) 지점을 1.25 V로 설정하여 온도 변화에 따른 성능 저하를 최소화하였다. 다양한 온도(300K~400K)에서 전류-전압 특성을 분석하여, ZTC 지점에서의 메모리 특성이 온도에 안정적으로 동작하는 것을 확인하였으며, 고온에서도 신뢰성 있는 동작을 보장하는 설계가 가능함을 입증하였다. 이를 통해 1T-DRAM 소자는 높은 신뢰성과 고효율을 갖춘 메모리 기술로서, 차세대 메모리 소자 개발에 중요한 기여를 할 수 있다.