• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.477-480
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• 2017

전기이중층 Capacitor는 대전력을 쉽게 충방전할 수 있는 전력저장장치로 순간전압강하 보상장치, 정전대책장치, 회생전력 흡수장치 등 적용하는 범위가 광범위하게 확대되고 있다. 전기이중층 Capacitor의 산업용 응용분야로서 제어회로 전원에 많이 사용되고 있는 ATX 전원의 Backup소자로서 전기이중층 Capacitor를 적용하고 있다. 본고에서는 ATX 전원에 전기이중층 Capacitor M-CAP을 응용한 사례를 소개하고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.625-631
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• 2014

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.727-730
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• 2001

Electrical wire explosion (EWE) is characterized by great current density and rapid metal heating, which make itself an ideal tool for nano-materials manufacturing technology. The EWE requires a high voltage electric-energy source. In the current experimental set-up a high voltage capacitor is used for the purpose. Hence, a power supply that is capable of charging the capacitor to a target voltage is required. One of the special requirements is the precise controllability of the stored energy level in the capacitor. Through this study a high voltage capacitor charger using a series resonant converter technology has been developed for the production of nanosize powder. A load capacitor of $32{\mu}F$ can be charged up to 20kV by the developed capacitor charger and discharged through a gap switch and a copper wire.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.313-316
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• 2000

This paper proposes a new solution by carrier-based SVPWM method to solve the most serious problem of Flying Capacitor Multi-level Inverter that is unbalance of capacitor voltages The voltage unbalance is occurred by the difference of each capacitor's charging and discharging time applied to Flying Capacitor Multi-level Inverter. It controls the variation of capacitor voltages into the mean'0' during some period by means of new carriers using the leg voltage redundancy in the Inverter. The solution can be easily expanded to the multi-level. Also this method can make the switching loss and conduction loss of device equal by the use of leg voltage redundancy. First the unbalance of capacitor voltage is analyzed and the conventional theory of self-balance using phase-shifted carrier is reviewed. And then the new method that is suitable to the Flying Capacitor Inverter is explained. The simulation results would be shown to verify the proposed method

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.3
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• pp.257-262
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• 2009

Capacitor is basically used for the power-factor compensation and sometimes as the passive filter to reduce harmonics of nonlinear load. Since the impedance of capacitor is inversely proportional to the frequency. The harmonic current may result in the problems of voltage distortion and resonance. Capacitor has easily fall under by two harmonic components, a nonlinear load and a distorted utility voltage. The amplified harmonic current and voltage may damage power capacitor. Hence the pre-investigation of harmonic is needed before designing and application the power factor for reducing fault rate. In this paper, we analyzed that voltage and current with harmonics components act on the capacitor under the resonance condition. we concluded that both voltage and current harmonics have an bad effect on the capacitor and current harmonics is a bitter rather than effect by voltage harmonics.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.6
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• pp.88-94
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• 2013

This paper proposes a capacitive touch switch using a switched-capacitor. The proposed method charges capacitance for measurement using the switched-capacitor until the voltage across the capacitance reaches a threshold voltage. As the proposed method uses the number of times being charged to measure the capacitance, the method has no relation with the operating frequency of the switched-capacitor. This paper also shows the quantization resolution of the proposed method is related to the capacitance in the switched-capacitor and the threshold voltage, i.e., the resolution is improved when the capacitance in the switched-capacitor is decreased and the threshold voltage is increased. Simulation result shows the method gives 31fF quantization resolution when the capacitance in the switched-capacitor is 50fF and threshold voltage is 80% of the supply voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.372-377
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• 2007

This paper proposes a novel fault diagnosis method of a electrolytic capacitor used for DC-link voltage smoothing in adjustable speed drives. The equivalent series resistance (ESR) of the electrolytic capacitor is directly estimated from DC-link voltage and load currents and the status of the electrolytic capacitor is determined from the estimated ESR. To compensate the variation of the ESR owing to temperature variation, diodes are located on the same PCB near the capacitor and the temperature of the capacitor is sensed indirectly from the voltage drop of diodes. Simulation and experimental studies show the effectiveness of the proposed method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.61-64
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• 2001

This study relates to a method for manufacturing a solid electrolytic capacitor using a functional polymer composition. The method comprises immersing the rolled aluminum electrolytic capacitor device in polyaniline solution with high electric conductivity to impregnate the device with polyaniline, drying the impregnated device in a drying oven which is maintained at constant temperature to fully remove the solvent, inserting the dried device to a capacitor aluminum can and then sealing with epoxy resin, to manufacture a solid electrolytic capacitor using a conducting polymer. As such, the impregnation can be performed well at not only normal temperature and pressure, but also high temperature and reduced pressure. The solid electrolytic capacitor has the advantages of high capacity, low impedance and low ESR, and also, low manufacturing cost, simple processes and high reliability.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.58-68
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• 1995

Polysilicon capacitors with pyrogenic oxide and TEOX oxide as insulators were fabricated to develop capacitors which can be applied to analog CMOS IC, and the characteristics of the capacitors were compared with each other. The morphology of bottom polysilicon in pyrogenic oxide capacitor is degraded due to the generaged protuberances of the polysilicon grain during oxidataion. The polysilican capacitor with pyrogenic oxide of 57 nm thickness showed that the effective potential barrier height of 0.45 eV is much less than that of MOS capacitor (3.2 eV)when the top electrode is biased with a positive volgate. The morphology of the polysilicon capacitor with TEOS oxide, however, was not degraded during oxide deposition by LPCVD. The polysilicon capacitor with TEOS oxide of 54 nm thickness showed the effective potential barrier height of 1.28 eV when the top electrode is biased with a negative voltage. Therefore, it is concluded that the polysilicon capacitor with TEOS oxide is more applicable to analog CMOS IC than the pyrogenic oxide polysilicon capacitor.