• Title/Summary/Keyword: Capacitance measurement

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The Optimization and Numerical Analysis of The Antenna Circuit for Antenna Design With 13.56MHz As Transmitting Wireless Power (무선전력 전송용 13.56MHz의 안테나 설계를 위한 안테나 회로의 최적화 및 수치적 해석)

  • Chung, Sung-In;Lee, Seung-Min;Lee, Hug-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.10
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    • pp.57-62
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    • 2009
  • This study proposes the optimization and numerical analysis of the antenna circuit for antenna design with 13.56 MHz as transmitting wireless power, for calculating the dose radiation exposure to the real time. The 13.56 MHz of the antenna frequency bands is used to the loop antenna which is a induced current for transmitting the power with wireless the reader to the tag. The study compared to the real measurement value as calculating the value of the inductance and capacitance through the numerical analysis for the antenna LC resonance using the theory of the electromagnetic induction method. We tried to search for the resonance point as the voltages of both sides of antenna coil by the scope measures of the peak point, as we tried to be variable the resonance capacitor for the optimization tuning of the antenna circuit and the matching of the antenna port. We convince our research contributes to help the design and application technology of the wireless power transmit system which is received power supply with wireless.

A Design of 1.42 - 3.97GHz Digitally Controlled LC Oscillator (1.42 - 3.97GHz 디지털 제어 방식 LC 발진기의 설계)

  • Lee, Jong-Suk;Moon, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.7
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    • pp.23-29
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    • 2012
  • The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

A Study on the Design of the Directional Coupler using Three Layer Microstrip Substrate (세 층 마이크로스트립 유전체 기판을 이용한 방향성 결합기 설계에 관한 연구)

  • 천동완;김원기;박정훈;김상태;신철재
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.4
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    • pp.513-520
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    • 2001
  • In this paper, the directional coupler using three layer microstrip substrate is proposed and the design method is notified. Modified re-entrant mode coupler is the proposed structure that one layer is added on upper plane of coupled transmission lines and the floating conductor is placed on added layer's upper planes. This structure has high coupling for the increase of odd mode capacitance and also has good performance in VSWR, isolation, phase difference because the difference of effective permittivity is small in each mode. We have designed the coupler from the calculation of impedance, effective permittivity, coupling coefficient using even, odd mode analysis method. From the simulation and measurement, proposed coupler has about 2 dB more tighter coupling than conventional coupler and also has good performance in VSWR, isolation, phase difference.

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An Unequal Power Divider with Adjustable Dividing Ratio (가변 분배 비율 비대칭 전력 분배기)

  • Lim, Jong-Sik;Oh, Seong-Min;Koo, Jae-Jin;Jeong, Yong-Chae;Ahn, Dal
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.5 s.120
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    • pp.478-485
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    • 2007
  • In this paper, an unequal 1:N Wilkinson power divider with adjustable dividing ratio is proposed. The proposed unequal power divider is composed of basic Wilkinson structure. It consists of rectangular-shaped defected ground structure (DGS), isolated island pattern in DGS, and varactor diodes of which capacitance depends on bias voltage. The characteristic impedance value of microstrip line having DGS goes up and down by controlling bias voltage for diodes, and consequently the power dividing ratio(N) is adjusted. The obtained N from measurement is $2.59{\sim}10.4$ which mean the proposed divider has adjustable unequal dividing ratio.

Design of Dual-Band Monopole Antenna Fed-by CPW Using Asymmetric Ground Plane (CPW 급전 비대칭 접지면을 이용한 이중 대역 모노폴 안테나 설계)

  • Lee, Sang-Min;Kim, Nam;Lee, Seung-Woo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.7
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    • pp.778-785
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    • 2010
  • The folded monopole antenna for applying mobile communications equipment and wireless devices is presented in this paper. By using the coplanar waveguide feed the operating bandwidth has improved. In addition, each individual resonant elements has occurred different capacitance through asymmetrical left and right ground planes; therefore, the bandwidth has kept and the impedance matching has stabilized. By measurement results, the impedance bandwidth under VSWR< 2.5:1 are $824{\sim}890$ MHz and the $1,500{\sim}2,170$ MHz, also radiation patterns has omni-directional characteristics. The maximum gains of the proposed antenna are 5.52, 0.64, 3.00, 0.94 and 1.85 dBi at 850, 1,575, 1,790, 1,930 and 2,050 MHz respectively. The proposed antenna will be adapted to the internal antenna of the mobile communication devices.

Study on the structure of buried type capacitor for MCM (Multi-Chip-Module) (MCM-C(Multi-Chip-Module)용 내장형 캐패시터의 구조적 특성에 관한 연구)

  • Yoo, C. S.;Lee, W. S.;Cho, H. M.;Lim, W.;Kwak, S. B.;Kang, N. K.;Park, J. C.
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.4
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    • pp.49-53
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    • 1999
  • In this study, the characteristics of the structure of buried type capacitor for RF multi- chip-module are investigated. We developed many kinds of structures to minimize the space of capacitor in module and the value of parastic series inductance without any loss in capacitance, and in this procedure the effect of vias especially position, size, number length are analyzed and optimized. This characteristics of structures are checked through HFSS(high frequency structure simulator) of HP, and the value of parastic series inductance is calculated by equivalent circuit analysis. And ensuing the result of simulation, we made buried type capacitors using LTCC (low temperature cofired ceramic) material. In measurement of this sample, we found out the effective and precise method can be applied to buried type and characteristics of vias and striplines added for measuring are quantified.

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Dynamic Range Extension of CMOS Image Sensor with Column Capacitor and Feedback Structure (컬럼 커패시터와 피드백 구조를 이용한 CMOS 이미지 센서의 동작 범위 확장)

  • Lee, Sanggwon;Jo, Sung-Hyun;Bae, Myunghan;Choi, Byoung-Soo;Kim, Heedong;Shin, Eunsu;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.24 no.2
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    • pp.131-136
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    • 2015
  • This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

The Electric Characteristics of Asymmetric Hybrid Supercapacitor Modules with Li4Ti5O11 Electrode (Li4Ti5O11 전극을 이용한 비대칭 하이브리드 슈퍼커패시터 전기적 모듈 특성)

  • Maeng, Ju-Cheul;Yoon, Jung-Rag
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.2
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    • pp.357-362
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    • 2017
  • Among the lithium metal oxides for asymmetric hybrid supercapacitor, $Li_4Ti_5O_{12}(LTO)$ is an emerging electrode material as zero-stain material in volume change during the with the charging and discharging processes. The pulverized LTO powder was observed to show the enhanced capacity from 120 mAh/g to 156 mAh/g at C-rate (10, 100 C). Hybrid supercapacitor module(48V, 416F) was fabricated using an asymmetric hybrid capacitor with a capacitance of 7500F. As a result of the measurement of C-rate characteristics, the module shows that the discharge time is drastically reduced at more than 50C, and the ESR and voltage drop characteristics are increased. The energy density and power density were reduced under high C-rate conditions. When designing asymmetric hybrid supercapacitor module, the C-rate and ESR should be considered As a result of measuring the 5 kw UPS, it was discharged at the current of 116A~170A during the discharge in the voltage range of 48V~30V, and the compensation time at discharge was measured to be about 33.2s. Experimental results show that it can be applied to applications related to stabilization of power quality by applying hybrid supercapacitor module.

Evaluation of the fabrications and properties of ultra-thin film for memory device application (메모리소자 응용을 위한 초박막의 제작 및 특성 평가)

  • Jeong, Sang-Hyun;Choi, Haeng-Chul;Kim, Jae-Hyun;Park, Sang-Jin;Kim, Kwang-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.169-170
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    • 2006
  • In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

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High Performance ESD/Surge Protection Capability of Bidirectional Flip Chip Transient Voltage Suppression Diodes

  • Pharkphoumy, Sakhone;Khurelbaatar, Zagarzusem;Janardhanam, Valliedu;Choi, Chel-Jong;Shim, Kyu-Hwan;Daoheung, Daoheung;Bouangeun, Bouangeun;Choi, Sang-Sik;Cho, Deok-Ho
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.4
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    • pp.196-200
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    • 2016
  • We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.