• 한국산학기술학회논문지
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• 제7권1호
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• pp.7-11
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• 2006

SCM(Scanning Capacitance Method)를 이용하여, SCM 팁의 전계에 의해 형성되는 실리콘내의 공핍영역를 분석할 수 있는 방법론을 구축하였다. 2차원 유한요소법을 이용하여 SCM으로 측정된 결과로부터 불순물의 농도를 도출할 수 있었다. 이 방법은 캐패시턴스, 공핍화된 체적 및 바이어스에 따른 캐패시턴스의 변화율로부터 구해진다. 본 연구에서는 팁의 크기, 산화층 두께 및 가해지는 바이어스에 따른 공핍 전하와 전위에 따른 영향등을 분석하였다.

• Advances in nano research
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• 제9권1호
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• pp.1-13
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• 2020

In this work, the electrical potential (EP) technique with an artificial neural networks (ANNs) for monitoring of nanostructures are used for the first time. This study employs an expert system to identify size and localize hidden nano-delamination (N.Del) inside layers of nano-pipe (N.P) manufactured from Basalt Fiber Reinforced Polymer (BFRP) laminate composite by using low-cost monitoring method of electrical potential (EP) technique with an artificial neural networks (ANNs), which are combined to decrease detection effort to discern N.Del location/size inside the N.P layers, with high accuracy, simple and low-cost. The dielectric properties of the N.P material are measured before and after N.Del introduced using arrays of electrical contacts and the variation in capacitance values, capacitance change and node potential distribution are analyzed. Using these changes in electrical potential due to N.Del, a finite element (FE) simulation model for N.Del location/size detection is generated by ANSYS and MATLAB, which are combined to simulate sensor characteristic, therefore, FE analyses are employed to make sets of data for the learning of the ANNs. The method is applied for the N.Del monitoring, to minimize the number of FE analysis in order to keep the cost and save the time of the assessment to a minimum. The FE results are in excellent agreement with an ANN and the experimental results available in the literature, thus validating the accuracy and reliability of the proposed technique.

• 대한화학회지
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• 제41권1호
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• pp.1-11
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• 1997

0.5 M $K_2SO_4$ 용액에서 여러 가지 세 탄소전극(glassy carbon, 인조흑연, graphite foil)에 대하여 양극분극에 따른 전극표면반응에 대한 연구를 임피던스 스펙트로스코피를 통하여 실시했다. Graphite foil 전극의 경우 이중츨 capacotance는 다른 두 전극재료에 비하여 높게 나타났으며, 양극분극시 glassy carbon과 인조 흑연(PVDF 혼합 graphite)은 전극계면에서 흡착현상에 의한 capacitance C의 영향이 현저하게 나타남을 알 수 있었다. 3종류 전극재료의 전기화학적 거동은 전극표면 조직의 차이에 의해 glassy carbon의 경우는 분극시 파라데이 임피던스의 영향을 받으며, graphite foil의 경우는 field transport의 지배를 받아 전압의 변화에 의한 임피던스 파라미터의 변화는 거의 나타나지 않았다.

• 공업화학
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• 제22권4호
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• pp.405-410
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• 2011

본 연구에서는 고용량 EDLC 전극의 제조를 위하여 전극의 활물질인 활성탄소에 $NF_3$ 가스를 이용하여 아미노불소화 반응을 유도하였다. 또한, 아미노불소화 반응에 의한 활성탄소의 기공 및 표면화학적 특성 변화와 그로부터 제조된 활성탄소전극의 비정전용량 특성 변화에 대하여 고찰하였다. 활성탄소의 아미노불소화 반응은 재료의 표면 기공특성을 저하시키지 않고 비표면적 및 기공부피 등의 기공특성을 유지시키면서 활성탄소의 표면에 전기화학적 특성의 향상에 도움이 되는 질소 및 불소 관능기를 효과적으로 도입시켰다. 1 at% 이하의 질소 및 불소 관능기가 도입된 활성탄소전극 (E-NF100AC)은 2 mV/s의 전압주사속도 조건에서 528 (${\pm}9$) F/g의 비정전용량으로 미처리 활성탄소전극(E-RAC)과 비교하여 약 122%의 용량증대효과를 나타내었다. 반면에, E-NF200AC의 조건에서는 1 at% 이상, 과량의 불소 관능기가 도입됨에 따라 E-NF100AC에 비하여 용량이 감소하였으며 이러한 결과로부터 적당량의 질소 및 불소 관능기 도입이 활성탄소전극의 비정전용량을 효과적으로 증가시킴을 확인할 수 있었다.

• 전기학회논문지P
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• 제58권4호
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• pp.476-482
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• 2009

This paper describes the development of capacitive sensor for the diagnosis of liquid dielectrics, which is widely used as the electrical insulating oil of transformer, circuit breaker, cable and etc. To survey the dielectric properties of the virgin and aged electrical insulating oils, we utilized the highly precise measuring system, using the principle of cross capacitance. The measured properties were used to determine the design factors of the sensor. Then the factors were optimized with the help of computational analysis. To evaluate diagnosis by the sensor, we performed accelerated thermal aging test about electrical insulating oils. The condition of aged specimens were investigated by measurements of relative permittivity i.e. capacitance change by capacitive sensor. And to evaluate the hysteresis characteristics with the change of temperature, we constructed a testing system, which was composed with vacuum drying oven, oil chamber and measuring instruments, such as LCR meter, MUX and so forth. Through the results of this investigation, we confirmed the superior characteristics of the newly developed sensor.

• 센서학회지
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• 제24권3호
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• pp.208-213
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• 2015

The purpose of this study is to optimize the design of a capacitive pressure sensor element using the simulation of electrical characteristics. The simulation of the ceramic sensor diaphragm ($Al_2O_3$) was performed by permitting pressure to change the curvature of the diaphragm. The pressure capacitance ($C_P$) was increased from 19.63 pF to 15.26 pF by applying pressure because the distance between the electrodes has been changed from $30{\mu}m$ to $15{\mu}m$. When the thickness of the diaphragm was changed to 0.46~0.52 mm, a larger capacitance change showed in accordance with the reduced thickness, which means an increase of sensitivity. However, considering the viewpoint of the signal linearity, it was selected for the optimum thickness of the diaphragm to 0.50 mm. The designed sensor element based on simulated results was tested to measure the output characteristics. Comparing of simulated and measured results, there was a margin of error of approximately 2%.

• 전자공학회논문지A
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• 제30A권7호
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• pp.82-88
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• 1993

This paper describes fabrication of relative type capacitive pressure sensor to be in great demand for many fields. The fabricated sensor consists of two parts` a sensing diaphragm and a pyrox glass cover. The sensor size is 4.5${\times}3.4mm$^{2})$ and 400$\mu$m thick. To improve the nonlinearity, this sensor is designed a rectangular silicon diaphragm with a center boss structure, and in order to improve the temperature characteristics of the sensor in a packaging process, the sensing element is mounted on the pyrex glass support. Some suggestions toward the design and fabrication of improved sensors have been presented. The zero pressure capacitance, Co of sensor is 26.57pF, and the change of capacitance, ${\Delta}$C is 1.55pF from 0Kgf/Cm$^{2}$ to 1Kgf/Cm$^{2}$ at room temperature. The nonlinearity of the sensor output with center boss diaphragm is 1.29%F.S., and thermal zero shift and thermal sensitivity shift is less than 1.43%F.S./$^{\circ}C$and 0.14% F.S./$^{\circ}C$, respectively.

• 한국정밀공학회지
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• 제22권4호
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• pp.52-59
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• 2005

When a micro hole is machined by EDM with a cylindrical electrode, the hole diameter is different at the inlet and the outlet of the micro hole. The taper shape of the micro hole is caused by not only wear of the electrode but the eroded particles. The eroded particles cause secondary discharge during machining the micro hole. As a result, the diameter of the inlet becomes larger than that of the outlet. In this paper, a new method is proposed to reduce the difference in diameter between the inlet and the outlet of the hole. Observed was that the feed depth and machining time affect the formation of taper shape On this experimental basis, ultrasonic vibration was applied to reduce machining time, and capacitance was changed during machining to use the difference in discharging energy of different capacitances. Using the proposed method, a straight micro-hole was fabricated.

• 한국산학기술학회논문지
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• 제10권1호
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• pp.91-95
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• 2009

나노튜브를 기반으로 한 용량성 나노 가속도계에 대한 특성을 고전적인 분자동역학 시뮬레이션을 이용하여 연구하였다 외부에서 공급된 힘을 이용하여 나노튜브의 위치를 제어할 수 있었고, 해당하는 위치에 의한 커패시턴스의 변화를 통하여 피드백 센싱을 할 수 있었다. 에너지 소모 측면을 고려하면, 나노 가속도계의 진동 특성은 초기 변위와는 무관하였으며, 이러한 측정 시스템은 진동하는 커패시턴스를 추적하여 가속도를 결정하고, 이것은 또한 공급된 힘과 용량성 힘, 반데르발스 힘, 결합력, 반발력과 같은 힘들이 균형을 이루는 위치를 결정할 수 있다.

• 대한전자공학회논문지
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• 제25권1호
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.