• Title/Summary/Keyword: Cache management

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A Study on Data Availability Improvement using Mobility Prediction Technique with Location Information (위치 정보와 이동 예측 기법을 이용한 데이터 가용성 향상에 관한 연구)

  • Yang, Hwan Seok
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.8 no.4
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    • pp.143-149
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    • 2012
  • MANET is a network that is a very useful application to build network environment in difficult situation to build network infrastructure. But, nodes that configures MANET have difficulties in data retrieval owing to resources which aren't enough and mobility. Therefore, caching scheme is required to improve accessibility and availability for frequently accessed data. In this paper, we proposed a technique that utilize mobility prediction of nodes to retrieve quickly desired information and improve data availability. Mobility prediction of modes is performed through distance calculation using location information. We used technique which global cluster table and local member table is managed by cluster head to reduce data consistency and query latency time. We compared COCA and CacheData and experimented to confirm performance of proposed scheme in this paper and efficiency of the proposed technique through experience was confirmed.

An On-chip Multiprocessor Miroprocessor with Shared MMU and Cache

  • Lee, Yong-Hwan;Jeong, Woo-Kyeong;An, Sang-Jun;Lee, Yong-Surk
    • Journal of Electrical Engineering and information Science
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    • v.2 no.4
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    • pp.1-7
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    • 1997
  • A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains tow IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. the IU is a 32-bit scalar processor expecially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. ETH SMPC is implemented in VLSI circuit by custom design and automated design tools.

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Improving Periodic Flush Overhead of File Systems Using Non-volatile Buffer Cache (비휘발성 버퍼 캐시를 이용한 파일 시스템의 주기적인 flush 오버헤드 개선)

  • Lee, Eunji;Kang, Hyojung;Koh, Kern;Bahn, Hyokyung
    • Journal of KIISE
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    • v.41 no.11
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    • pp.878-884
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    • 2014
  • File I/O buffer cache plays an important role in narrowing the wide speed gap between the main memory and the secondary storage. However, data loss or inconsistencies may occur if the system crashes before the data that has been updated in the buffer cache is flushed to storage. Thus, most operating systems adopt a daemon that periodically flushes dirty data to the secondary storage. In this study, we show that periodic flushes account for 30-70% of the total write traffic to storage and remove this inefficiency by implementing a small, non-volatile buffer cache. Specifically, we present space-efficient management techniques, such as delta-write and fragment-grouping, and show that the storage write traffic and throughput can be improved by a margin of 44.2% and 23.6%, respectively, with only a small NVRAM.

Improvement of Handoff-state and QOS in Wireless Environment

  • Jeong, You-Sun;Choe, U-Gin
    • Journal of information and communication convergence engineering
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    • v.8 no.1
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    • pp.1-5
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    • 2010
  • In this paper, we propose for improving QoS in wireless micro cellular network using Cellular-IP/PRC(Paging Route Cache) with Paging Cache and Route Cache in Cellular-IP and propose for performance of realtime and non-real time handoff service using Handoff state machine Paging Route Cache. Although the Cellular-IP/PRC technology is devised for mobile internet communication, it bas its vulnerability in frequent handoff environment. On the other hand, Cellular IP combines the capability of cellular networks to provide high performance handoff and efficient location management of active and idle mobile users with the inherent flexibility, robustness and scalability found in IP networks. Also Cellular-IP/PRC use semi-soft handoff. During semi-soft hand off a mobile host may be in contact with either of the old and new base stations and receive packets from them. Packets intended to the mobile node are sent to both base stations and buffered, so when the mobile host eventually moves to the new location it can continue to receive packets without interruption. It should be suitable for realtime service such as multimedia traffic. But, much waste of resource will occur in this method, especially for non-real time services such as FTP and E-mail. Therefore, a new algorithm that performs different handoff according to characteristic of each traffic by use of reserved field in IP packet is proposed in this thesis. This hand off state machine using differentiated handoff improves quality of services in Cellular-IP/PRC. Suggested algorithm shows better performance than existing technology in wireless mobile internet communication environment. Matlab simulation results are improving QoS, show call drop and call blocking provided to Paging Router Cache during handoff state machine in Cellular-IP/PRC.

MLC-LFU : The Multi-Level Buffer Cache Management Policy for Flash Memory (MLC-LFU : 플래시 메모리를 위한 멀티레벨 버퍼 캐시 관리 정책)

  • Ok, Dong-Seok;Lee, Tae-Hoon;Chung, Ki-Dong
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.1
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    • pp.14-20
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    • 2009
  • Recently, NAND flash memory is used not only for portable devices, but also for personal computers and server computers. Buffer cache replacement policies for the hard disks such as LRU and LFU are not good for NAND flash memories because they do not consider about the characteristics of NAND flash memory. CFLRU and its variants, CFLRU/C, CFLRU/E and DL-CFLRU/E(CFLRUs) are the buffer cache replacement policies considered about the characteristics of NAND flash memories, but their performances are not better than those of LRD. In this paper, we propose a new buffer cache replacement policy for NAND flash memory. Which is based on LFU and is taking into account the characteristics of NAND flash memory. And we estimate the performance of hit ratio and flush operation numbers. The proposed policy shows better hit ratio and the number of flush operation than any other policies.

Disk Cache Manager based on Minix3 Microkernel : Design and Implementation (Minix3 마이크로커널 기반 디스크 캐쉬 관리자의 설계 및 구현)

  • Choi, Wookjin;Kang, Yongho;Kim, Seonjong;Kwon, Hyeogsoong;Kim, Jooman
    • Journal of Digital Convergence
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    • v.11 no.11
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    • pp.421-427
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    • 2013
  • Disk Cache Manager(DCM), a functional server of microkernel based, to improve the I/O power of shared disks is designed and implemented in this work. DCM interfaces other different servers with message passing through ports by serving as a system actor the multi-thread mode on the Minix3 micro-kernel. DCM proposed in this paper uses the shared disk logically as a Seven Disk and Sodd Disk to enable parallel I/O. DCM enables the efficient placement of disk data because it raises disk cache hit-ratio by increasing the cache size when the utilization of the particular disk is high. Through experimental results, we show that DCM is quite efficient for a shared disk with higher utilization.

Low-Power Data Cache Architecture and Microarchitecture-level Management Policy for Multimedia Application (멀티미디어 응용을 위한 저전력 데이터 캐쉬 구조 및 마이크로 아키텍쳐 수준 관리기법)

  • Yang Hoon-Mo;Kim Cheong-Gil;Park Gi-Ho;Kim Shin-Dug
    • The KIPS Transactions:PartA
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    • v.13A no.3 s.100
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    • pp.191-198
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    • 2006
  • Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

Authenticated Handoff with Low Latency and Traffic Management in WLAN (무선랜에서 낮은 지연 특성을 가지는 인증유지 핸드오프 기법과 트래픽 관리 기법)

  • Choi Jae-woo;Nyang Dae-hun;Kang Jeon-il
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.15 no.2
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    • pp.81-94
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    • 2005
  • Recently, wireless LAN circumstance is being widely deployed in Public spots. Many People use Portable equipments such as PDA and laptop computer for multimedia applications, and also demand of mobility support is increasing. However, handoff latency is inevitably occurred between both APs when clients move from one AP to another. To reduce handoff latency. in this paper, we suggest WFH(Weighted Frequent Handoff) using effective data structure. WFH improves cache hit ratio using a new cache replacement algorithm considering the movement pattern of users. It also reduces unessential duplicate traffics. Our algorithm uses FHR(Frequent Handoff Region) that can change pre-authentication lesion according to QoS based user level, movement Pattern and Neighbor Graph that dynamically captures network movement topology.

Flash-Aware Transaction Management Scheme for flash Memory Database (플래시 메모리 데이터베이스를 위한 플래시인지 트랜잭션 관리 기법)

  • Byun Si Woo
    • Journal of Internet Computing and Services
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    • v.6 no.1
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    • pp.65-72
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    • 2005
  • Flash memories are one of best media to support portable computers in mobile computing environment. The features of non-volatility, low power consumption. and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However. we need to Improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal. we devise a new scheme called flash-aware transaction management (FATM). FATM improves transaction performance by exploiting SRAM and W-Cache, We also propose a simulation model to show the performance of FATM. Based on the results of the performance evaluation, we conclude that FATM scheme outperforms the traditional scheme.

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