• Title/Summary/Keyword: Cache data

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A MAC System Design for High-speed UWB SoC (고속 UWB SoC의 MAC 시스템 설계)

  • Kim, Do-Hoon;Wee, Jeong-Wook;Lee, Chung-Yong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.4
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    • pp.1-5
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    • 2011
  • We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.

Content Centric Networking Naming Scheme for Efficient Data Sharing (효율적인 데이타 교환을 위한 Content-Centric Networking 식별자 방안)

  • Kim, Dae-Youb
    • Journal of Korea Multimedia Society
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    • v.15 no.9
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    • pp.1126-1132
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    • 2012
  • To enhance network efficiency, CCN allow intermediate network nodes between a content consumer and a content publisher to temporarily cache transmitted contents. Then the network nodes immediately return back the cached contents to another consumers when the nodes receives relevant contents request messages from the consumers. For that, CCN utilizes hierarchical content names to forward a request message as well as a response message. However, such content names semantically contain much information about domain/user as well as content itself. So it is possible to invade users' privacy. In this paper, we first review both the problem of CCN name in the view point of privacy and proposed schemes. Then we propose an improved name management scheme for users' privacy preservation.

Efficient Content-based Load Distribution for Web Server Clusters (웹 서버 클러스터를 위한 효율적인 내용 기반의 부하 분배)

  • Chung Ji Yung;Kim Sungsoo
    • Journal of KIISE:Information Networking
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    • v.32 no.1
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    • pp.60-67
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    • 2005
  • A cluster consists of a collection of interconnected stand-alone computers working together and provides a high-availability solution in application area such as web services or information systems. Content-based load distribution for web server clusters uses the detailed data found in the application layer to intelligently route user requests among web servers. In this paper, we propose a content-based load distribution algorithm that considers cache hit and load information of the web servers under the web server clusters. In addition, we expand this algorithm in order to manage user requests for dynamic file. Specially, our algorithm does not keep track of any frequency of access information or try to model the contents of the caches of the web servers.

A Real-Time JPEG2000 Codec Implementation on ARM9 Processor (ARM9 프로세서용 실시간 JPEG2000 코덱의 구현)

  • Kim, Young-Tae;Cho, Shi-Won;Lee, Dong-Wook
    • Journal of the Institute of Convergence Signal Processing
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    • v.8 no.3
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    • pp.149-155
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    • 2007
  • In this paper, we propose an real-time implementation of JPEG2000 codec on the ARM9 processor. The implemented codec is designed to separate control codes from data management codes in order to use effectively the system resources such as processor and memory. Especially, in embedded situations like cellular phones it is very important to provide good services using limited processor and internal memory. Since ARM9 series processors do not provide floating-point, large amount of computational time is required to perform the operation which needs highly repetitive floating-point computations like DWT(discrete wavelet transform). The proposed codec was programed using fixed-point to overcome this weakness. Also code optimization considering cache memory was applied to further improve the computational speed.

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Heat & Cool Injection Molded Fresnel Lens Solar Concentrators (가열-냉각 사출성형 방식을 적용한 집광형 프레넬렌즈)

  • Jeong, Byeong-Ho;Min, Wan-Ki;Lee, Kang-Yeon
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.63 no.4
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    • pp.283-289
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    • 2014
  • A Fresnel lens is an optical component which can be used as a cost-effective, lightweight alternative to conventional continuous surface optics. Fresnel lens solar concentrators continue to fulfill a market requirement as a system component in high volume cost effective Concentrating Photovoltaic (CPV) electricity generation. The basic principles of the fresnel lens are reviewed and some practical examples are described. To investigate the performance space of the Fresnel lens, a fast simulation method which is a hybrid between raytracing and analytical computation is employed to generate a cache of simulation data. Injection molders are warming up to the idea of cycling their tool surface temperature during the molding cycle rather than keeping it constant. Heat and cool process are now also finding that raising the mold wall temperature above the resin's glass-transition or crystalline melting temperature during the filling stage and product performance in applications from automotive to packaging to optics. This paper deals with the suitability of Fresnel lenses of imaging and non-imaging designs for solar energy concentration. The concentration fresnel lens confirmed machinability and optical transmittance and roughness measure through manufactured the prototype.

Design and Implementation of MPOA using SDL (SDL을 이용한 MPOA 설계 및 구현)

  • Lim, Ji-Young;Kim, Hee-Jung;Lim, Soo-Jung;Chae, Ki-Joon;Lee, Mee-Jung;Choi, Kil-Young;Kang, Hun
    • Journal of KIISE:Computing Practices and Letters
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    • v.6 no.6
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    • pp.643-656
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    • 2000
  • MPOA proposed and standardized by the ATM Forum is a protocol tllat provides effective bridging and routing for ATM networks in a diverse network environment. Its plimary goal is to transfer unicast data effectively among the subnets. In this paper, MPOA components are implemented using the SDL(Specification and Description Language) which the ITU has standardized for the development of communication systems. In addition, MPOA procedures for various operations such as address translation for packets from upper layers, Ingress/Egress cache management and shortcut configuration, are examined with tlle help of the SDT(SDL Design Too]) simulator.

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The Load Balancing Destage Algorithm of RAID5 Controller using Reference History (참조 정보를 이용한 RAID5 제어기의 부하 균형 반출 기법)

  • Jang, Yun-Seok;Kim, Bo-Yeon
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.3
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    • pp.776-787
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    • 2000
  • Write requests which stored in disk cache of the RAID5 controller should be destaged to disk arrays according to the destage algorithm. As the response performance of the parallel IO request is being hit by the effect of the destage, several destage algorithms have been studied to enhance the performance of he RAID5 controller. Among the destage algorithms, the load balancing destage algorithm has better performance than other destage algorithms when system load is highly increased. But the load balancing destage algorithm gives priority to load balance among the disks in disk arrays, therefore, when some disks are affected by the very heavy system load caused by small data requests, the load balancing destage algorithm cannot enhance the performance of parallel IO requests effectively since it makes effort to maintain the load balance without the benefit of the locality of the write requests. This paper proposes a new RAID5 controller that applied reference-load balancing destage algorithm which decides the destage priority based on the reference history and load distribution of the disks. The simulation results show that RAID5 controller with the reference-load balancing destage algorithm has better performance than previous load balancing destage algorithm.

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The Simulation of High-Speed Forwarding IP Packet with ATM Switch (ATM 스위치를 이용한 IP 패킷 고속 전송 시뮬레이션)

  • Heo, Kang-Woo;Lee, Myung-Ho
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.10
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    • pp.2764-2771
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    • 1999
  • ATM has recently received much attention because of its high capacity, its bandwidth scalability, and its ability to support multiservice traffic. However, ATM is connection oriented whereas the vast majority of modern data networking protocols are connectionless. The alternative to support current service on ATM will be a router with attached switching hardware that has the ability to cache routing decisions. In this paper, we described the router using a switch and simulated the performance. From the results of the simulation, the routing delay was decreased as the number of flow channels. Cell-delay was shortest at 30,000 cell-time when the keeping time of a flow channel was. The line utilization was rapidly decrease when a flow-setup time is 20 30 cell-time. The results of this simulation could be applied to predict the performance of the router using ATM switch.

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Mechanism to Select the Data Source of HDFS with SSD Cache Based on Storage I / O Cost (SSD 캐시를 적용한 HDFS의 I/O 비용 기반 데이터 선택 기법)

  • Kim, Minkyung;Shin, Mincheol;Park, Sanghyun
    • Proceedings of the Korea Information Processing Society Conference
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    • 2015.04a
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    • pp.676-679
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    • 2015
  • 빅데이터 분석을 위한 Hadoop 환경에서 고성능 저장장치인 SSD에 대한 중요성이 증가하면서 일반적으로 사용되는 저장장치인 HDD와 혼합하여 사용하는 연구들이 주목 받고 있다. 특히 SSD를 HDD의 캐시로 사용했을 때 저장장치에 대한 I/O 성능을 향상할 수 있다는 연구 결과들이 있다. 본 연구는 이를 바탕으로 SSD를 HDD의 캐시로 사용한다. HDFS는 저장장치에 접근하여 I/O를 수행하는데 기존에는 로컬 서버에서 캐시 미스가 발생한 경우 로컬 HDD로 접근한다. 이러한 방식은 접근하는 데이터에 따라 SSD의 높은 Bandwidth를 활용하지 못하게 되는 경우를 발생시키고 그 결과 특정 서버의 I/O 지연으로 전체 분산 처리의 성능을 저하시킬 수 있다. 이를 해결하기 위해 본 연구는 HDFS 레벨에서 로컬 서버의 HDD와 데이터 복제본들이 저장된 원격 서버의 SSD에서 I/O를 수행하는 경우에 대해 수식을 통해 비용을 비교한다. 그 결과 항상 기대 성능이 높은 저장 장치를 선택하여 데이터를 읽어오게 함으로써 기존 방식보다 성능이 개선될 수 있음을 입증한다.

Memory-Efficient High Performance Parallelization of Aho-Corasick Algorithm on Intel Xeon Phi (Intel Xeon Phi 에서의 Aho-Corasick 알고리즘을 위한 메모리 친화적인 고성능 병렬화)

  • Tran, Nhat-Phuong;Jeong, Yosang;Lee, Myungho
    • Proceedings of the Korea Information Processing Society Conference
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    • 2014.04a
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    • pp.87-89
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    • 2014
  • Aho-Corasick (AC) algorithm is a multiple patterns string matching algorithm commonly used in many applications with real-time performance requirements. In this paper, we parallelize the AC algorithm on the Intel's Many Integrated Core (MIC) Architecture, Xeon Phi Coprocessor. We propose a new technique to compress the Deterministic Finite Automaton structure which represents the set of pattern strings again which the input data is inspected for possible matches. The new technique reduces the cache misses and leads to significantly improved performance on Xeon Phi.