• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.692-699
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• 2015

Evarything as a Service (XaaS) is a software, platform, infra distribution method which provide users with necessary modules, not entire modules, as a service. To efficiently and securely operate services such as XaaS, it is needed to solve various Internet problems like network congestion, weak security and so on. Future Internet technologies are provided to solve such problems. Specially, named data networking architecture (NDN) proposes that network nodes cache transmitted data, and then they send the cached data if receiving request messages for the cached data. So NDN can efficiently diffuse excessive request messages transmitted toward original contents providers. However, when receiving contents through NDN, receivers can not confirm the practical providers because the practical providers can be different from original contents providers. Hence, it is requested for receivers to verify the received contents and such a verification process can cause service delay of XaaS. In this paper, we improve a content verification scheme of NDN to enhance the performance of services such as XaaS.

• Journal of KIISE
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• v.43 no.7
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• pp.820-826
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• 2016

There is a growing requirement for big data processing which extracts valuable information from a large amount of data. The Hadoop system employs the MapReduce framework to process big data. However, MapReduce has limitations such as inflexible and slow data processing. To overcome these drawbacks, SQL query processing techniques known as SQL-on-Hadoop were developed. Apache Tajo, one of the SQL-on-Hadoop techniques, was developed by a Korean development group. External merge sort is one of the heavily used algorithms in Tajo for query processing. The performance of external merge sort in Tajo is influenced by two parameters, sort buffer size and fanout. In this paper, we analyzed the performance of external merge sort in Tajo with various sort buffer sizes and fanouts. In addition, we figured out that there are two major causes of differences in the performance of external merge sort: CPU cache misses which increase as the sort buffer size grows; and the number of merge passes determined by fanout.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.154-160
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• 2014

The address resolution protocol (ARP) provides dynamic mapping between two different forms of addresses: the 32-bit Internet protocol (IP) address of the network layer and the 48-bit medium access control (MAC) address of the data link layer. A host computer finds the MAC address of the default gateway or the other hosts on the same subnet by using ARP and can then send IP packets. However, ARP can be used for network attacks, which are one of the most prevalent types of network attacks today. In this study, a new ARP algorithm that can prevent IP spoofing attacks is proposed. The proposed ARP algorithm is a broadcast ARP reply and an ARP notification. The broadcast ARP reply was used for checking whether the ARP information was forged. The broadcast ARP notification was used for preventing a normal host's ARP table from being poisoned. The proposed algorithm is backward compatible with the current ARP protocol and dynamically prevents any ARP spoofing attacks. In this study, the proposed ARP algorithm was implemented on the Linux operating system; here, we present the test results with respect to the prevention of ARP spoofing attacks.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05b
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• pp.1209-1212
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• 2003

오늘날 인터넷 환경에서의 망은 유무선의 환경이 통합된 하나의 망으로 달수 있다. 일반적인 TCP에서는 무선망에서의 핸드오프나 비트오류 등으로 인한 패킷 손실이 발생하는 경우에도 흔잡제어 알고리즘으로 손실된 패킷을 복구하게 되며 이러한 복구는 혼잡윈도우를 줄이게 됨으로 인해 현저히 TCP의 처리량을 감소시키게 된다. 본 논문에서는 유무선이 통합된 망에서 데이터 전송 효율을 높일 수 있는 알고리즘을 제시하고자 한다. 이 알고리즘에서는 홈서버를 사용하여 무선망에서 발생한 패킷 손실이 종단간의 재전송이 아닌 홈서버에서 지역 재전송을 함으로써 유무선망의 부하를 줄이고 흔잡제어 알고리즘이 실행되는 것을 방지하여 TCP의 성능향상을 가져올 수 있으며 캐쉬메모리에 재전송 패킷을 보관하여 재전송함으로써 보다 빠른 재전송효과를 얻을 수 있다.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.231-240
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• 2002

This paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing independently scheduled VLIW instructions. Aggressively Packed VLIW (APVLIW) processor is aimed specifically at independent scheduling Very Long Instruction Word(VLIW) instructions with dependency information. The APVLIW processor independently schedules earth instruction within long instructions using functional unit and dynamic scheduler pairs. Every dynamic scheduler dynamically checks far data dependencies and resource collisions while scheduling each instruction. This scheduling is especially effective in applications containing loops. We simulate the architecture and show that the APVLIW processor performs significantly better than the VLIW processor for a wide range of cache sizes and across various numerical benchmark applications.

• Convergence Security Journal
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• v.6 no.4
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• pp.91-99
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• 2006

Generally, a study of web caching is conducted on a performance improvement with structural approaches and a new hybrid method using existing methods, and studies on caching method itself. And existing analysis of reference-characteristic are conducted on a history analysis and a preference of users, a view point of data mining by log analysis. In this study, we analyze the reference-characteristic of web object on a view point of a characteristic of probability-distribution and a mean value of lifetime of a web-object. And using this result, we propose the new method for a performance improvement of a web-caching.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.129-132
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• 2002

AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.683-692
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• 1995

Many kinds of large scale multiprocessing and parallel-processing systems have recently been developed. The contention on the shared data caused by multiple processors may degrade system performance. So, processor synchronization has become one of the important issues in these systems. To solve the synchornization issues, a lot of software and hardware schemes based on spin lock have been proposed. Although software schemes are easy to implement, hardware schemes are preferred in many systems to gain optimized performance. This paper proposes an efficient processor synchronization scheme, called QCX,and describes its design considerations, hardware, algorithm, protocol. Also, in this paper, the performance of QCX has been evaluated with QOLB[5] and LBP[7] using a simulation. The simulation, with varying the number of processor and the contention on shared variables, measured the average execution times of a workload. The simulation results show that the performances of QCX is best when practicability is considered. QCX is more efficient than QOLB and LBP in two aspects. First, the hardware of QCX is more simple and cost-effective because the cache structure need not be changed. Secondly, QCX is more general because it uses a generic atomic instruction.

• Journal of the Korea Society of Computer and Information
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• v.9 no.4 s.32
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• pp.167-172
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• 2004

Although Mobile IP proposed in IETF is effective. it has inefficiency in case mobile hosts communicate with each others while they are roaming frequently in a specific area. It occurs lots of latency because mobile hosts must be registered and establish an secure path under the internet emvironments and transmitting data on the path. Additionally this inefficiency is more aggravated in case mobile hosts has high mobility. Thus this paper propose a method using Anchor foreign agent by Anchor chain method which combine an pointer forwarding and a cache method plus a border router as a way to complement the above problem which exists in an mobility management in a specific area.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.4
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• pp.1-5
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• 2011

We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.