• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.353-359
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• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• The KIPS Transactions:PartA
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• v.16A no.1
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• pp.27-34
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• 2009

Recently, power saving with high performance is one of the hot issues in the mobile systems. Various technologies are introduced to achieve low-power processors, which include sub-micron semiconductor fabrication, voltage scaling, speed scaling and etc. In this paper, we introduce a new method that reduces of energy loss at the data cache. Our methods take the benefits in terms of speed and energy loss using selective way precharging of way prediction with concurrent way selecting. By the simulation results, our method achieves 10.2% energy saving compared to the way prediction method, and 56.4% energy saving compared to the common data cache structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.1
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• pp.222-236
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• 2019

Wireless content caching in small cell networks has recently been considered as a promising way to alleviate the congestion of the backhaul in emerging heterogenous cellular network. However, how to select files which are cached in SBSs and how to make SBSs work together is an important issue for cooperative cache research for the propose of reducing file download time. In this paper, a Cooperative-Greedy strategy (CGS) among cache-enabled small base stations (SBSs) in small cell network is proposed, in order to minimize the download time of files. This problem is formulated as a Chinese restaurant game.Using this game model, we can configure file caching schemes based on file popularity and the spectrum resources allocated to several adjacent SBSs. Both the existence and uniquencess of a Nash equilibrium are proved. In the theoretical analysis section, SBSs cooperate with each other in order to cache popular files as many as possible near UEs. Simulation results show that the CGS scheme outperforms other schemes in terms of the file-download time.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.285-294
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• 2003

The request scheduling algorithms being used for the cluster web servers are mostly in two categories : load-balancing and contents-based cache affinity The goal of the load-balancing algorithms is to balance the loads between real servers. On the other hand, contents-based scheduling algorithm exploits the cache affinity in a way that the same type of requests are to be directed to a dedicated real server allowing load imbalance. So the performance comparison of the two algorithms is necessary, nevertheless the related experiment results are not much suggested. In this paper, performance evaluations have been done to compare the performance of the two scheduling algorithms. To accomplish this, we first implement a linux cluster web server, and then present the performance measurement results. The main contribution of this paper is to help the cluster web server administrators to select an algorithm fitting in with their circumstances from the two algorithms.