• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1302-1308
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• 2005

Propose Cellular-IP/PRC network with united paging and Cellular IP special duality that use roof information administration cache to secure lake acceptance method in wireless Internet environment and QoS in lesser extent cell environment. When speech quality is secured considering increment of interference to receive in case of suppose that proposed acceptance method grooves base radio station capacity of transfer node is plenty, and moat of contiguity cell transfer node was accepted at groove base radio station with a blow, groove base radio station new trench lake acceptance method based on transmission of a message electric power estimate of transfer node be. Do it so that may apply composing PC(Paging Cache) and RC(Routing Cache) that was used to manage paging and router in radio Internet network in integral management and all nodes as one PRC(Paging Router Cache), and add hand off state machine in transfer node so that can manage hand off of transfer node and Roaming state efficiently, and studies so that achieve connection function at node. Analyze benevolent person who influence on telephone traffic in system environment and forecasts each link currency rank and imbalance degree, forecast most close and important lake interception probability and lake falling off probability, GoS(Grade of Service), efficiency of cell capacity in QoS because applies algorithm proposing based on algorithm use gun send-receive electric power that judge by looking downward link whether currency book was limited and accepts or intercept lake and handles and displays QoS performance improvement.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.461-476
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• 2003

Due to the implementation ease and alleviation of memory bottleneck effect, NUMA architecture has dominated in the multiprocessor systems for the past several years. However, because the NUMA system distributes memory in each node, frequent remote memory access is a key factor of performance degradation. Therefore, efficient design of RAC(Remote Access Cache) in NUMA system is critical for performance improvement. In this paper, we suggest Multi-Grain RAC which can adaptively control the RAC line size, with respect to each application behavior Then we simulate NUMA system with multi-grain RAC using MINT, event-driven memory hierarchy simulator. and analyze the performance results. At first, with profile-based determination method, we verify the optimal RAC line size for each application and, then, we compare and analyze the performance differences among NUMA systems with normal RAC, with optimal line size RAC, and with multi-grain RAC. The simulation shows that the worst case can be always avoided and results are very close to optimal case with any combination of application and RAC format.

• The KIPS Transactions:PartD
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• v.11D no.2
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• pp.293-304
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• 2004

Recently, caching for the database-backed web applications has received much attention. The results of frequent queries could be cached for repeated reuse or for efficient processing of the relevant queries. Since the emergence of XML as a standard for data exchange on the web, today's web applications are to retrieve information from the remote XML sources across the network, and thus it is desirable to maintain the XML query results in the cache for the web applications. In this paper, we describe implementation of an XML query processing system that supports cache-answerability of XML queries, and evaluate its performance. XML path expression, which is one of the core features of XML query languages including XQuery, XPath, and XQL was considered as the XML query. Their result is maintained as an XML materialized view in the XML cache. The algorithms to rewrite the given XML path expression using its relevant materialized view proposed in [13] were implemented with RDBMS as XML store. The major issues of implementation are described in detail. The results of performance experiments conducted with the implemented system showed effectiveness of cache-answerability of XML queries. Comparison with previous research in terms of performance is also Provided.

• Journal of computational fluids engineering
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• v.19 no.2
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• pp.24-29
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• 2014

In this study, a parallel performance of CUPID-code has been investigated for both Ethernet and Infiniband network system to examine the effect of cache memory and network-speed. Bi-conjugate gradient solver of CUPID-code has been parallelised by using domain decomposition method and message passing interface (MPI). It is shown that the parallel performance of Ethernet-network system is worse than that of Infiniband-network system due to the slow network-speed and a small cache memory. It is also found that the parallel performance of each system deteriorates for a small problem due to the communication overhead, but the performance of Infiniband-network system is better than Ethernet-network system due to a much faster network-speed. For a large problem, the parallel performance depends less on network system.

• The Transactions of the Korea Information Processing Society
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• v.7 no.12
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• pp.3964-3975
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• 2000

There are two policies for maintaining consistency among the multiple processor caches in a multiprocessor system: Write invalidate and Write update. In the write invalidate policy, whenever a processor attempt to write its cached block, it has to invalidate all the same copies of the updated block in the system. As a results of this frequent invalidations, this policy results in high cache miss ratio. On the other hand, the write update policy renew them, instead of invalidating all the same copies. This policy has to transfer the updated contents through interconnection network, whether the updated block is ptivate or not. Therefore the network suffer from heavy transaction traffic. In this paper we present an efficient cache coherence protocol for shared memory multiprocessor system connected by slotted ring. This protocol is based on the write update policy, but the updated contents are transferred only in case of updating the shared block. Otherwise, if the updated block is private, the updated contents are not transferred. We analyze the proposed protocol and enforce simulation to compare it with previous version.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.893-901
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• 2013

This paper suggests a method of developing live media streaming service through Linux server system on android system environment. The android application constructed in the experiment is able to record media while sending it to Linux server. Generated real time media data is send to linux server through Multipart Request class of Apache Tomcat server constructed on Linux system. Also in this research, by utilizing Android video player and media player class, development of android application structures was accomplished, which has methods of; playing live media stream data on video server, or playing live media stream data while saving stream data in cache. The structure and function of suggested system and application is confirmed by series of experiments.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.643-657
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• 2004

The chordal ring based CC-NUMA system contains many links to transmit transactions between a local node and a remote node because of its structural characteristics. However, the inclination that the transactions concentrate on the ring link increases both the traffic of the ring link and the response time, which degrades the overall performance of the chordal ring based CC-NUMA system. In this paper we suggest a new remote cache replacement policy that considers both the number of total links and the number of ring links to traverse for the transactions. Our proposed replacement policy can balance data between the ring link and the chordal link properly because it reflects the characteristics of chordal ring based CC-NUMA system well.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.221-228
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• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.243-246
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• 2007

집합-연관 캐쉬는 직접-사상 캐쉬보다 적중률이 높다는 장점이 있는 반면, 전력 소모가 많다는 단점이 있다. 그러한 단점을 보완하기 위해 웨이-프리딕팅 셋-어소시에이티브 캐쉬, 로케이션 캐쉬 시스템 등의 연구들이 계속 되어왔다. 본 논문에서는 로케이견 캐쉬 시스템에서 생각할 수 있는 논점들을 살펴보고, 이를 효율적으로 극복할 수 있는 스피시픽-웨이 캐쉬 시스템을 제안하였다. 또한 Simplescalar와 MiBench를 이용하여 스피시픽-웨이 캐쉬 시스템의 성능을 측정하였고, 그 결과 39.6%의 예상-적중률이 나타난 것으로 확인되었다.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.6
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• pp.383-391
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• 2011

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.