• Title/Summary/Keyword: CVD(chemical vapor deposition)

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Characterization of structural properties of CNTs grown by ICP-CVD (ICP-CVD 방법을 이용한 탄소나노튜브의 제작 및 물성분석)

  • Chang, Seok-Mo;Kim, Young-Do;Park, Chang-Kyun;Uhm, Hyun-Seok;Park, Jin-Seok
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.1533-1535
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    • 2002
  • Carbon nanotubes (CNTs) were grown with high density on a large area of Ni-coated silicon oxide substrates by using an inductively coupled plasma-chemical vapor deposition (ICP-CVD) of $C_2H_2$ at temperatures ranging from 600 to $700^{\circ}C$. The Ni catalyst was formed using an RF magnetron sputtering system with varying the operating pressure and exposure time of $NH_3$ plasma. The surface morphology of nickel catalyst films and CNTs was examined by SEM and AFM. The graphitized structure of CNTs was confirmed by Ramman spectra, SEM, and TEM. The growth of CNTs was observed to be strongly influenced by the surface morphology of Ni catalyst, which depended on the pre-treatment time and growth temperature. Dense CNTs with uniform-sized grains were successfully grown by ICP-CVD.

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Double Layer (Wet/CVD $SiO_2$)의 Interface Trap Density에 대한 연구

  • Lee, Gyeong-Su;Choe, Seong-Ho;Choe, Byeong-Deok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.340-340
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    • 2012
  • 최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

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No Tilt Angle Dependence of Grain Boundary on Mechanical Strength of Chemically Deposited Graphene Film

  • Kim, Jong Hun;An, Sung Joo;Lee, Jong-Young;Ji, Eunji;Hone, James;Lee, Gwan-Hyoung
    • Journal of the Korean Ceramic Society
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    • v.56 no.5
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    • pp.506-512
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    • 2019
  • Although graphene has been successfully grown in large scale via chemical vapor deposition (CVD), it is still questionable whether the mechanical properties of CVD graphene are equivalent to those of exfoliated graphene. In addition, there has been an issue regarding how the tilt angle of the grain boundary (GB) affects the strength of graphene. We investigate the mechanical properties of CVD graphene with nanoindentation from atomic force microscopy and transmission electron microscopy. Surprisingly, the samples with GB angles of 10° and 26° yielded similar fracture stresses of ~ 80 and ~ 79 GPa, respectively. Even for samples with GB exhibiting a wider range, from 0° to 30°, only a slightly wider fracture stress range (~ 50 to ~ 90 GPa) was measured, regardless of tilt angle. The results are contrary to previous studies that have reported that GBs with a larger tilt angle yield stronger graphene film. Such a lack of angle dependence of GB can be attributed to irregular and well-stitched GB structures.

Analysis on the Flow and Heat Transfer in a Large Scale CVD Reactor for Si Epitaxial Growth (Si 선택적 성장을 위한 대형 CVD 반응기 내의 열 및 유동해석)

  • Jang, Yeon-Ho;Ko, Dong Guk;Im, Ik-Tae
    • Journal of the Semiconductor & Display Technology
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    • v.15 no.1
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    • pp.41-46
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    • 2016
  • In this study, gas flow and temperature distribution in the multi-wafer planetary CVD reactor for the Si epitaxial growth were analyzed. Although the structure of the reactor was simplified as the first step of the study, the three-dimensional analysis was performed taking all these considerations of the revolution of the susceptor and the rotation of satellites into account. From the analyses, a reasonable velocity field and temperature field were obtained. However, it was found that analyses including the upper structure of the reactor were required in order to obtain more realistic temperature results. DCS mole fraction above the satellite surface and the susceptor surface without satellite was compared in order to check the gas species mixing. We found that satellite rotation helped gases to mix in the reactor.

Characteristics of Ni/SiC Schottky Diodes Grown by ICP-CVD

  • Gil, Tae-Hyun;Kim, Han-Soo;Kim, Yong-Sang
    • KIEE International Transactions on Electrophysics and Applications
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    • v.4C no.3
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    • pp.111-116
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    • 2004
  • The Ni/SiC Schottky diode was fabricated with the $\alpha$-SiC thin film grown by the ICP-CVD method on a (111) Si wafer. $\alpha$-SiC film has been grown on a carbonized Si layer in which the Si surface was chemically converted to a very thin SiC layer achieved using an ICP-CVD method at $700^{\circ}C$. To reduce defects between the Si and $\alpha$-SiC, the surface of the Si wafer was slightly carbonized. The film characteristics of $\alpha$-SiC were investigated by employing TEM (Transmission Electron Microscopy) and FT-IR (Fourier Transform Infrared Spectroscopy). Sputterd Ni thin film was used as the anode metal. The boundary status of the Ni/SiC contact was investigated by AES (Auger Electron Spectroscopy) as a function of the annealing temperature. It is shown that the ohmic contact could be acquired beyond a 100$0^{\circ}C$ annealing temperature. The forward voltage drop at 100A/cm was I.0V. The breakdown voltage of the Ni/$\alpha$-SiC Schottky diode was 545 V, which is five times larger than the ideal breakdown voltage of the silicon device. As well, the dependence of barrier height on temperature was observed. The barrier height from C- V characteristics was higher than those from I-V.

A Study on Nanocrystalline Silicon Thin Film Deposited by ICP-CVD (ICP-CVD로 증착된 미세결정 실리콘 박막의 특성에 관한 연구)

  • Kim, Sun-Jae;Park, Joong-Hyun;Han, Sang-Myeon;Park, Sang-Geun;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 2006.07c
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    • pp.1303-1304
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    • 2006
  • 본 연구에서는 ICP-CVD (inductively coupled plasma chemical vapor deposition)를 이용해 미세결정 실리콘 (nanocrystalline silicon thin film transistor, ns-Si TFT) 초기 성장 단계에 발생하는 비정질의 Incubation layer를 줄이기 위한 실험을 수행하였다. ICP-CVD를 사용하여 증착한 Si-rich $SiN_x$ Seed layer 상의 미세절정 실리콘의 성막조건을 알아보고 특성을 평가하였다. 미세결정 실리콘 박막은 Raman Spectroscopy를 이용해 분석하였다. 미세결정 실리콘의 초기 성장 단계에 발생하는 비정질 Incubation layer를 줄이기 위하여 Si-rich $SiN_x$를 Seed layer로 사용하는 것이 효과적임을 확인하였다. 또한 Si-rich $SiN_x$ 위에서의 미세결정 실리콘 표면 형태와 Seed 성장 기회의 관계를 알아보았다. 높은 전압의 수소 플라즈마 처리는 Seed 성장 기회를 늘이고, 박막의 결정화도를 높임을 확인하였다. 얇은 Incubation layer를 가지는 35nm 이하 두께의 미세결정 실리콘이 성공적으로 증착되었다. 본 연구 결과는 bottom 게이트 방식 박막 트랜지스터에 증착되는 미세결정 실리콘의 전기적 특성 향상에 유용할 것으로 판단된다.

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A study for properties of AZO thin film prepared to Ar-plasma treatment using ICP-CVD (ICP-CVD에 의해 Ar 플라즈마 처리된 AZO 박막의 표면 거칠기에 관한 연구)

  • Bang, Tae-Bok;Ryu, Sung-Won;Kim, Deok-Su;Cho, Do-Hyun;Rhee, Byung-Roh;Kim, Jong-Jae;Park, Seoung-Hwan;Hong, Woo-Phyo;Kim, Hwa-Min
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.386-387
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    • 2007
  • ICP-CVD(Inductively Coupled Plasma-Chemical Vapor Deposition)를 이용하여 플라즈마 처리에 따른 Al이 도핑된 ZnO(AZO) 박막의 표면 부착력과 굴절율, 표면거칠기에 관한 연구를 하였다. 플라즈마 처리는 인가전압, 시간을 변수로 하였고 반응 가스는 Ar을 사용하였다. 표면조성은 AFM, 광학적 특성은 UV-Vis 분광계를 이용한 광투과도 측정으로부터 굴절률과 밴드갭을 조사하였고 표면 부착력은 접촉각 분석기(제조사:Kruss)를 사용하여 조사하였다. 플라즈마 처리 시간이 길어짐에 따라 박막 표면의 거칠기가 커지고 부착력은 증가하는 것으로 나타났다.

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Swift Synthesis of CVD-graphene Utilizing Conduction Heat Transfer

  • Kim, Sang-Min;Mag-isa, Alexander E.;Oh, Chung-Seog;Kim, Kwang-Seop;Kim, Jae-Hyun;Lee, Hak-Joo;Yoon, Jonghyuk;Lee, Eun-Kyu;Lee, Seung-Mo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.652-652
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    • 2013
  • The conventional thermal chemical vapor deposition (CVD) setup for the graphene synthesis has mainly used convective heat transfer in order to heat a catalyst (e.g. Cu) up to $1,000^{\circ}C$. Although the conventional CVD has been so far widely accepted as the most appropriate candidate enabling mass-production of high-quality graphene, this method has stillremained under the standard for the commercialization largely due to the poor productivity arisen out of the required long processing time. Here, we introduced a fast and efficient synthetic route toward CVD-graphene. Unlike the conventional CVD using convection heat transfer, we adopted a CVD setup utilizing conduction heat transfer between Cu catalyst and rapid heating source. The high thermal conductive nature of Cu and the employed rapid heating source led to the remarkable reduction in processing timeas compared to the conventional convection based CVD (Fig. 1A), moreover, the synthesized graphene was turned out to have comparable quality to that synthesized by the conventional CVD (Fig. 1B). For the optimization of the conduction based CVD process, the parametric studies were thoroughly performed using through Raman spectroscopy and electrical sheet resistance measurement. Our approach is thought to be worth considerable in order to enhance productivity of the CVD graphene in the industry.

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Patterning of CVD Diamond Films For MEMS Application

  • Wang, Xiaodong;Yang, Yirong;Ren, Congxin;Mao, Minyao;Wang, Weiyuan
    • Journal of the Korean Vacuum Society
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    • v.7 no.s1
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    • pp.167-170
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    • 1998
  • To apply diamond films in microelectromechanical systems(MEMS), it is necessary to develop the patterning technologies of diamond films in the micrometer scale. In this paper, three different kinds of technologies for patterning CVD diamond films carried out by us were demonstrated: selective growth by improved diamond nucleation in DC bias-enhanced microwave plasma chemical vapor deposition (MPCVD) system, selective growth of seeding using diamond-particle-mixed photoresist, and selective etching of oxygen ion beam using Al as the mask. It was show that high selectivity and precise patterns had been achieved, and all the processes were compatible with IC process.

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Graphene Synthesis by Low Temperature Chemical Vapor Deposition and Rapid Thermal Anneal (저온 화학기상증착법 및 급속가열 공정을 이용한 그래핀의 합성)

  • Lim, Sung-Kyu;Mun, Jeong-Hun;Lee, Hi-Deok;Yoo, Jung-Ho;Yang, Jun-Mo;Wang, Jin-Suk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.12
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    • pp.1095-1099
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    • 2009
  • As a substitute material for silicon, we synthesized few layer graphene (FLG) by CVD process with a 300-nm-thick nickel film deposited on the silicon substrate and found out the lowest temperature for graphene synthesis. Raman spectroscopy study showed that the D peak (wave length : ${\sim}1,350\;cm^{-1}$) of graphene was minimized and then the 2D one (wave length : ${sim}2,700\;cm^{-1}$) appeared when rapid thermal anneal is carried out with the $C_2H_2$ treated nickel film. This study demonstrates that a high quality FLG formed at a low temperature of $400^{\circ}C$ is applicable as CMOS devices and transparent electrode materials.