• 제목/요약/키워드: CS코어

검색결과 19건 처리시간 0.022초

Genetic Algorithm-based Hardware Resource Mapping Technique for the latency optimization in Wireless Network-on-Chip (무선 네트워크-온-칩에서 지연시간 최적화를 위한 유전알고리즘 기반 하드웨어 자원의 매핑 기법)

  • Lee, Young Sik;Lee, Jae Sung;Han, Tae Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 한국정보통신학회 2016년도 춘계학술대회
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    • pp.174-177
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    • 2016
  • Wireless network-on-chip (WNoC) can alleviate critical path problem of existing typical NoCs by integrating radio-frequency module on router. In this paper, core-connection-aware genetic algorithm-based core and WIR mapping methodology at small world WNoC is presented. The methodology could optimize the critical path between cores with heavy communication. The 33% of average latency improvement is achieved compared to random mapping methodology.

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Application Core Mapping to Minimize the Network Latency on Regular NoC Architectures (규칙적인 NoC 구조에서의 네트워크 지연 시간 최소화를 위한 어플리케이션 코어 매핑 방법 연구)

  • Ahn, Jin-Ho;Kim, Hong-Sik;Kim, Hyun-Jin;Park, Young-Ho;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제45권4호
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    • pp.117-123
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    • 2008
  • In this paper, we propose a novel ant colony optimization(ACO)-based application core ma ins method for implementing network-on-chip(NoC)-based systems-on-chip(SoCs). The proposed method efficiently put application cores to a mesh-type NoC satisfying a given design objective, the network latency. Experimental results using a functional circuit including 12 cores show that the proposed algorithm can produce near optimal mapping results within a second.

A Novel Test Scheduling Algorithm Considering Variations of Power Consumption in Embedded Cores of SoCs (시스템 온 칩(system-on-a-chip) 내부 코어들의 전력소모 변화를 고려한 새로운 테스트 스케쥴링 알고리듬 설계)

  • Lee, Jae-Min;Lee, Ho-Jin;Park, Jin-Sung
    • Journal of Digital Contents Society
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    • 제9권3호
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    • pp.471-481
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    • 2008
  • Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

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Design of Enhanced IEEE 1500 Wrapper Cell and Interface Logic For Transition Delay Fault Test (천이 지연 고장 테스트를 위한 개선된 IEEE 1500 래퍼 셀 및 인터페이스 회로 설계)

  • Kim, Ki-Tae;Yi, Hyun-Bean;Kim, Jin-Kyu;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제44권11호
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    • pp.109-118
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    • 2007
  • As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

A Study of a Task Mapping Technique for heterogeneous MPSoCs (이기종 MPSoC 를 위한 태스크 매핑 기법 연구)

  • Cho, Jungseok;Jung, Youjin;Cho, Doosan
    • Annual Conference of KIPS
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    • 한국정보처리학회 2014년도 춘계학술발표대회
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    • pp.18-19
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    • 2014
  • 멀티프로세서 시스템 온칩 (MPSoC) 플랫폼은 고성능 임베디드 시스템을 위한 핵심 구성요소이다. MPSoC 를 구성하는 각각의 처리요소 (processing element, PE)는 대응하는 태스크의 연산 특징에 맞춤으로 최적화되어 있어야 한다. 갈수록 증가하는 고성능의 요구에 따라 동종 MPSoC 는 각각의 태스크 연산 특징에 최적화된 다양한 PE 를 보유한 이기종 MPSoC 로 발전되어 왔다. 따라서 이기종 MPSoC 의 코어들은 응용에 특화된 맞춤형 명령어 세트로 설계된다. 하지만 이러한 이기종성은 다양한 태스크로 구성된 응용들을 어떻게 서로 다른 특성을 지닌 PE 들에 매핑해야 최적의 시스템을 구성할 지를 결정해야 하는 부담을 컴파일러와 같은 툴에 지우고 있다. 잘못된 매핑은 시스템 성능을 현저히 저하시킬 소지가 있다. 본 연구에서는 멀티미디어 응용 태스크의 연산 패턴을 분석하여 최적의 태스크 매핑을 결정하는 기법을 제안하고 있다.

Development of Cesium-selective Paramagnetic Core Inorganic Composite Agent for Water Decontamination (수질오염 제염을 위한 세슘 선택성 상자성 코어 무기복합제염제 개발)

  • Seong Pyo Hong;Bo-Sun Kang
    • Journal of Radiation Industry
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    • 제18권2호
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    • pp.127-132
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    • 2024
  • Large amounts of liquid radioactive waste or radioactive contaminated water could be produced during the treatment of radiation accidents or during the dismantling and decontamination process of nuclear power plants. Since most of the decontamination agents to date are difficult to recover after adsorption of radioactive isotopes, their use in open environments such as rivers, reservoirs, or oceans is limited. In this study, as a radioactive decontamination agent that can overcome the current limitations when used in an open environment, a paramagnetic core inorganic composite (PMCIC) decomposite agent with high selectivity to cesium ions was developed. PMCore was prepared by synthesizing paramagnetic iron oxide nanoparticles, and inorganic crystals such as metal-ferrocyanide were conjugated to the surface so that PMCore could be selective to cesium ions. The developed PMCIC could be easily recovered from the water by magnetism and could adsorb up to 94 μM of Cs atoms per 1 g of PMCIC.

Clay Mineralogy and Geochemistry of a Sediment Core from the Seamount to the South of Antarctic Polar Front, Drake Passage (남극 드레이크해협 극전선 남부 해산 퇴적물 코어의 점토광물 및 지구화학적 특성)

  • Jeong, Gi-Young
    • Journal of the Mineralogical Society of Korea
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    • 제19권3호
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    • pp.163-169
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    • 2006
  • Mineralogy and geochemistry of the sediment core from the seamount (2710 m below the sea level) just south of the Antarctic Polar Front were examined to draw paleoceanographic information in glacial-interglacial cycles. Smectite was most abundant clay mineral associated with illite and chlorite. Its content was slightly higher below 170 cm, suggesting a boundary between isotope stage 4 and 5. Si, Zr, Cs, Th, REE, $K_{2}O$, and $Al_{2}O_{3}$ show complete antithetical distribution with respect to $CaCO_{3}$ through the core. $SiO_{2}$ maxima and $CaCO_{3}$ minima at depths of 24, 136, and 176 cm are probably correlated with massive influx of ice-rafted debris during the advance of Antarctic ice shelves. Ni, Cu, and Ba show rather little correlation with $SiO_{2}$, suggesting their relation to biogenic debris, precipitation from seawater, or hydrothermal input. Particularly, Ba maxima tend to lag $10{\sim}20cm$ after $SiO_{2}$ maxima, probably due to rapid increase of productivity following deglaciation.

An Efficient Repair Method to Reduce Area Overhead by Sharing Bitmap Memory (비트맵 메모리 공유를 통해 면적을 크게 줄인 효율적인 수리 방법)

  • Cho, Hyungjun;Kang, Sungho
    • Journal of the Institute of Electronics and Information Engineers
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    • 제49권9호
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    • pp.237-243
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    • 2012
  • In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.