• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1713-1718
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• 2004

It has been known that 1/f noise of MOSFET is generated by the superposition of single random telelgraph signals (RTS). In this study, jitters caused by 1/f noise of MOSFET are analysed with RTS supplied to all of the nodes of the CMOS ring oscillator under investigation. Through the analysis of the variations of jitters and jitter ratios with varying values of the amplitude of RTS, it is found that the jitters and the jitter ratios are proportional to the amplitude of RTS. And the analysis of FFT of the outputs of the ring oscillator reveals that the jitters are closely related to the phase noise of the high order harmonics of the ring oscillator outputs.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.185-189
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• 2017

This paper proposes a low power frequency divider for an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) was designed, along with a current-mode logic (CML) frequency divider in order to obtain a broadband and high-frequency operation. A ring oscillator was designed to operate at 1.2 GHz, and the ILFD was used to divide the frequency of its input signal by two. The structure of the ILFD is similar to that of the ring oscillator in order to ensure the frequency alignment between the oscillator and the ILFD. The CML frequency divider was used as the second stage of the divider. The proposed frequency divider was applied in a conventional PLL design, using a 0.18 ${\mu}m$ CMOS process. Simulation shows that the proposed divide-by-two ILFD and the divide-by-eight CML frequency dividers operated as expected for an input frequency of 1.2 GHz, with a power consumption of 30 mW.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.184-186
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• 2005

The effect of power supply noise on the phase noise of a ring oscillator is studied. The power supply noise source in series with DC power supply voltage is applied to a 3 stage CMOS ring oscillator. The phase noise due to the power supply noise is modeled by the narrow band phase modulation. The model is verified by the fact that the spectrum of output of ring oscillator has two side bands at the frequencies offset from the frequency of the ring oscillator by the frequency of the power supply noise source. Simulations at several different frequency of the power supply noise reveals that the ring oscillator acts as a low pass filter to the power supply noise. This study, as a result, shows that the phase noise generated by the power supply noise is inversely proportional to the frequency offset from the carrier frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.6-12
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• 2006

Recently, according to the rapid development of mobile system, the development of relative mobile components has been required, and especially, with the miniaturization of mobile component, the complex with nearby components has been progressed. In this paper, multi-output VC-TCXO (Voltage Controlled-Temperature Compensated Crystal Oscillator) for WCDMA integrates the additional CMOS inverter, so it can be the normal clipped sinewave output and additional CMOS output, and also it can be satisfied the VC-TCXO's requirements for WCDMA system. And the important characteristics of reference oscillator, like phase noise and frequency short term stability, are satisfied with WCDMA(UMTS) system's requirement In this paper, however, 25MHz is used for reference frequency, similarly and practically, we think that it can be used from 10MHz to 40MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2273-2277
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• 2010

In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.103-106
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• 2003

An oscillatory neural network circuit has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed oscillatory neural network consists of 3 neural oscillator cells with excitatory synapses and a neural oscillator cell with inhibitory synapse. Simulations of a network of oscillators demonstrate cooperative computation. Measurements of the fabricated chip in condition of $\pm$ 2.5 V power supply is shown.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.179-182
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• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.68-74
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• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.